forked from OSchip/llvm-project
[mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, DAHI, DATI, DEXT, DEXTM and DEXTU instructions
Differential Revision: http://reviews.llvm.org/D10923 llvm-svn: 244744
This commit is contained in:
Zoran Jovanovic
parent
0c8beb1c95
commit
366783e14c
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@ -847,7 +847,7 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
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if (hasMips32r6()) {
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DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableMicroMips32r632, Instr, Insn, Address,
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Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
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this, STI);
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} else {
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DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
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@ -855,6 +855,7 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
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Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
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this, STI);
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}
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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@ -283,7 +283,7 @@ class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
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//
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "MicroMips32r6" in {
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let DecoderNamespace = "MicroMipsR6" in {
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def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
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def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
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def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
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@ -0,0 +1,70 @@
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//=- MicroMips64r6InstrFormats.td - Instruction Formats -*- tablegen -* -=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes microMIPS64r6 instruction formats.
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//
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//===----------------------------------------------------------------------===//
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class DAUI_FM_MMR6 {
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bits<5> rt;
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bits<5> rs;
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bits<16> imm;
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bits<32> Inst;
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let Inst{31-26} = 0b111100;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-0} = imm;
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}
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class POOL32I_ADD_IMM_FM_MMR6<bits<5> funct> {
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bits<5> rs;
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bits<16> imm;
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bits<32> Inst;
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let Inst{31-26} = 0b010000;
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let Inst{25-21} = funct;
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let Inst{20-16} = rs;
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let Inst{15-0} = imm;
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}
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class POOL32S_EXTBITS_FM_MMR6<bits<6> funct> {
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bits<5> rt;
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bits<5> rs;
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bits<5> size;
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bits<5> pos;
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bits<32> Inst;
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let Inst{31-26} = 0b010110;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = size;
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let Inst{10-6} = pos;
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let Inst{5-0} = funct;
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}
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class POOL32S_DALIGN_FM_MMR6 {
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bits<5> rs;
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bits<5> rt;
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bits<5> rd;
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bits<3> bp;
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bits<32> Inst;
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let Inst{31-26} = 0b010110;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-8} = bp;
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let Inst{7-6} = 0b00;
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let Inst{5-0} = 0b011100;
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}
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@ -0,0 +1,98 @@
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//=- MicroMips64r6InstrInfo.td - Instruction Information -*- tablegen -*- -=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes MicroMips64r6 instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// Instruction Encodings
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//
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//===----------------------------------------------------------------------===//
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class DAUI_MMR6_ENC : DAUI_FM_MMR6;
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class DAHI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10001>;
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class DATI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10000>;
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class DEXT_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b101100>;
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class DEXTM_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b100100>;
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class DEXTU_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b010100>;
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class DALIGN_MMR6_ENC : POOL32S_DALIGN_FM_MMR6;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Descriptions
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//
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//===----------------------------------------------------------------------===//
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class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
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list<dag> Pattern = [];
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}
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class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd>;
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class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
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string Constraints = "$rs = $rt";
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}
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class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd>;
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class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd>;
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class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
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SDPatternOperator Op = null_frag> : MMR6Arch<instr_asm>, MipsR6Inst {
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dag OutOperandList = (outs RO:$rt);
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dag InOperandList = (ins RO:$rs, PosOpnd:$pos, size_ext:$size);
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
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list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
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InstrItinClass Itinerary = II_EXT;
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Format Form = FrmR;
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string BaseOpcode = instr_asm;
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}
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class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm6,
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MipsExt>;
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class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm6,
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MipsExt>;
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class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm6,
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MipsExt>;
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class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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Operand ImmOpnd> : MMR6Arch<instr_asm>, MipsR6Inst {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
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list<dag> Pattern = [];
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}
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class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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//
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "MicroMipsR6" in {
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def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
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def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6;
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def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6;
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def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DEXTU_MM64R6 : StdMMR6Rel, DEXTU_MMR6_DESC, DEXTU_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DALIGN_MM64R6 : StdMMR6Rel, DALIGN_MMR6_DESC, DALIGN_MMR6_ENC,
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ISA_MICROMIPS64R6;
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}
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@ -276,9 +276,11 @@ def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
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let isCodeGenOnly = 1 in
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def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
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def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
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def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
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def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
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def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
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def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
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}
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def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
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def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
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@ -81,10 +81,12 @@ class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
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//
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//===----------------------------------------------------------------------===//
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def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
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def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
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def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
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def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
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let AdditionalPredicates = [NotInMicroMips] in {
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def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
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def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
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def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
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def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
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}
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def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
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def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
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def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
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@ -186,6 +186,8 @@ def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
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AssemblerPredicate<"!FeatureMips64r6">;
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def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
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AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
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def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
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AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
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def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
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AssemblerPredicate<"FeatureMips16">;
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def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
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@ -255,6 +257,9 @@ class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
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class ISA_MICROMIPS32R6 {
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list<Predicate> InsnPredicates = [HasMicroMips32r6];
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}
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class ISA_MICROMIPS64R6 {
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list<Predicate> InsnPredicates = [HasMicroMips64r6];
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}
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// The portions of MIPS-III that were also added to MIPS32
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class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
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@ -1981,3 +1986,7 @@ include "MicroMipsInstrFPU.td"
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// Micromips r6
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include "MicroMips32r6InstrFormats.td"
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include "MicroMips32r6InstrInfo.td"
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// Micromips64 r6
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include "MicroMips64r6InstrFormats.td"
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include "MicroMips64r6InstrInfo.td"
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@ -228,6 +228,7 @@ public:
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}
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bool inMicroMipsMode() const { return InMicroMipsMode; }
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bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
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bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
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bool hasDSP() const { return HasDSP; }
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bool hasDSPR2() const { return HasDSPR2; }
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bool hasMSA() const { return HasMSA; }
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@ -0,0 +1,15 @@
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# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips64r6 -mattr=micromips | FileCheck %s
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0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5
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0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4
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0x42 0x03 0x00 0x04 # CHECK: dati $3, 4
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0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7
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0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 7
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0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 3, 7
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0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5
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