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[AMDGPU][MC][GFX11] Correct ds_swizzle_b32 

Enable offset parsing.

Differential Revision: https://reviews.llvm.org/D127404
This commit is contained in:
Dmitry Preobrazhensky 2022-06-14 12:56:38 +03:00
parent 3397236c4e
commit 365d827f65
3 changed files with 43 additions and 6 deletions
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10
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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@ -6291,6 +6291,7 @@ void AMDGPUAsmParser::cvtDSOffset01(MCInst &Inst,
void AMDGPUAsmParser::cvtDSImpl(MCInst &Inst, const OperandVector &Operands, void AMDGPUAsmParser::cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
bool IsGdsHardcoded) { bool IsGdsHardcoded) {
OptionalImmIndexMap OptionalIdx; OptionalImmIndexMap OptionalIdx;
AMDGPUOperand::ImmTy OffsetType = AMDGPUOperand::ImmTyOffset;
for (unsigned i = 1, e = Operands.size(); i != e; ++i) { for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
@ -6308,13 +6309,10 @@ void AMDGPUAsmParser::cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
// Handle optional arguments // Handle optional arguments
OptionalIdx[Op.getImmTy()] = i; OptionalIdx[Op.getImmTy()] = i;
}
AMDGPUOperand::ImmTy OffsetType = if (Op.getImmTy() == AMDGPUOperand::ImmTySwizzle)
(Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_gfx10 || OffsetType = AMDGPUOperand::ImmTySwizzle;
Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_gfx6_gfx7 || }
Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_vi) ? AMDGPUOperand::ImmTySwizzle :
AMDGPUOperand::ImmTyOffset;
addOptionalImmOperand(Inst, Operands, OptionalIdx, OffsetType); addOptionalImmOperand(Inst, Operands, OptionalIdx, OffsetType);

27
llvm/test/MC/AMDGPU/gfx11_ds.s
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@ -125,3 +125,30 @@ ds_sub_gs_reg_rtn v[5:6], v255 offset:127 gds
ds_sub_gs_reg_rtn v[5:6], v255 gds ds_sub_gs_reg_rtn v[5:6], v255 gds
// GFX11: encoding: [0x00,0x00,0xee,0xd9,0x00,0xff,0x00,0x05] // GFX11: encoding: [0x00,0x00,0xee,0xd9,0x00,0xff,0x00,0x05]
ds_swizzle_b32 v8, v2
// GFX11: encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
ds_swizzle_b32 v8, v2 offset:0
// GFX11: encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
ds_swizzle_b32 v8, v2 offset:0xFFFF
// GFX11: encoding: [0xff,0xff,0xd4,0xd8,0x02,0x00,0x00,0x08]
ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3)
// GFX11: encoding: [0xe4,0x80,0xd4,0xd8,0x02,0x00,0x00,0x08]
ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,16)
// GFX11: encoding: [0x1f,0x40,0xd4,0xd8,0x02,0x00,0x00,0x08]
ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,8)
// GFX11: encoding: [0x1f,0x1c,0xd4,0xd8,0x02,0x00,0x00,0x08]
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,4,1)
// GFX11: encoding: [0x3c,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,8,7)
// GFX11: encoding: [0xf8,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "01pip")
// GFX11: encoding: [0x07,0x09,0xd4,0xd8,0x02,0x00,0x00,0x08]

12
llvm/test/MC/Disassembler/AMDGPU/ds_gfx11.txt
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@ -3817,6 +3817,18 @@
# GFX11: ds_swizzle_b32 v5, v1 offset:swizzle(BITMASK_PERM,"00p00") ; encoding: [0x04,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05] # GFX11: ds_swizzle_b32 v5, v1 offset:swizzle(BITMASK_PERM,"00p00") ; encoding: [0x04,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
0x04,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05 0x04,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05
# GFX11: ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM,0,1,2,3) ; encoding: [0xe4,0x80,0xd4,0xd8,0x02,0x00,0x00,0x08]
0xe4,0x80,0xd4,0xd8,0x02,0x00,0x00,0x08
# GFX11: ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,4) ; encoding: [0x1f,0x10,0xd4,0xd8,0x02,0x00,0x00,0x08]
0x1f,0x10,0xd4,0xd8,0x02,0x00,0x00,0x08
# GFX11: ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,16) ; encoding: [0x1f,0x3c,0xd4,0xd8,0x02,0x00,0x00,0x08]
0x1f,0x3c,0xd4,0xd8,0x02,0x00,0x00,0x08
# GFX11: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,32,1) ; encoding: [0x20,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
0x20,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08
# GFX11: ds_swizzle_b32 v5, v255 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05] # GFX11: ds_swizzle_b32 v5, v255 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05 0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05