forked from OSchip/llvm-project
[ARM/AArch64] Relocate and update InterleavedAccessPass tests (NFC)
The interleaved access pass is an IR-to-IR transformation that runs before code generation. It matches interleaved memory operations to target-specific intrinsics (that are later lowered to load and store multiple instructions on ARM/AArch64). We place tests for similar passes (e.g., GlobalMergePass) under test/Transforms. This patch moves the InterleavedAccessPass tests out of test/CodeGen and into target-specific directories under test/Transforms/InterleavedAccess. Although the pass is an IR pass, many of the existing tests were llc tests rather opt tests. For example, the tests would check for ldN/stN instructions generated by llc rather than the intrinsic calls the pass actually inserts. Thus, this patch updates all tests to be opt tests that check for the inserted intrinsics. We already have separate CodeGen tests that ensure we lower the interleaved access intrinsics to their corresponding ldN/stN instructions. In addition to migrating the tests to opt, this patch also performs some minor clean-up (to ensure consistent naming, etc.). Differential Revision: https://reviews.llvm.org/D29184 llvm-svn: 293309
This commit is contained in:
Matthew Simpson
parent
32b9600a7e
commit
3650df13be
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@ -1,86 +0,0 @@
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; RUN: opt < %s -mtriple=aarch64 -interleaved-access -S | FileCheck %s
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; CHECK-LABEL: @extract_user_basic(
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; CHECK: %ldN = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32
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; CHECK: %[[R:.+]] = extractvalue { <4 x i32>, <4 x i32> } %ldN, 0
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; CHECK: extractelement <4 x i32> %[[R]], i64 1
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define void @extract_user_basic(<8 x i32>* %A, i1 %C) {
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entry:
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%L = load <8 x i32>, <8 x i32>* %A, align 8
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%S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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br i1 %C, label %if.then, label %if.merge
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if.then:
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%E = extractelement <8 x i32> %L, i32 2
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br label %if.merge
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if.merge:
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ret void
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}
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; CHECK-LABEL: @extract_user_multi(
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; CHECK: %ldN = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32
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; CHECK: %[[R:.+]] = extractvalue { <4 x i32>, <4 x i32> } %ldN, 0
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; CHECK: extractelement <4 x i32> %[[R]], i64 0
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; CHECK: extractelement <4 x i32> %[[R]], i64 1
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define void @extract_user_multi(<8 x i32>* %A, i1 %C) {
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entry:
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%L = load <8 x i32>, <8 x i32>* %A, align 8
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%S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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br i1 %C, label %if.then, label %if.merge
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if.then:
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%E1 = extractelement <8 x i32> %L, i32 0
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br label %if.merge
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if.merge:
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%E2 = extractelement <8 x i32> %L, i32 2
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ret void
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}
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; CHECK-LABEL: @extract_user_multi_no_dom(
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; CHECK-NOT: %ldN = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32
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define void @extract_user_multi_no_dom(<8 x i32>* %A, i1 %C) {
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entry:
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%L = load <8 x i32>, <8 x i32>* %A, align 8
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%E1 = extractelement <8 x i32> %L, i32 0
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br i1 %C, label %if.then, label %if.merge
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if.then:
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%S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%E2 = extractelement <8 x i32> %L, i32 2
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br label %if.merge
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if.merge:
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ret void
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}
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; CHECK-LABEL: @extract_user_wrong_const_index(
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; CHECK-NOT: %ldN = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32
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define void @extract_user_wrong_const_index(<8 x i32>* %A) {
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entry:
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%L = load <8 x i32>, <8 x i32>* %A, align 8
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%S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%E = extractelement <8 x i32> %L, i32 1
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ret void
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}
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; CHECK-LABEL: @extract_user_undef_index(
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; CHECK-NOT: %ldN = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32
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define void @extract_user_undef_index(<8 x i32>* %A) {
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entry:
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%L = load <8 x i32>, <8 x i32>* %A, align 8
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%S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%E = extractelement <8 x i32> %L, i32 undef
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ret void
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}
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; CHECK-LABEL: @extract_user_var_index(
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; CHECK-NOT: %ldN = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32
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define void @extract_user_var_index(<8 x i32>* %A, i32 %I) {
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entry:
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%L = load <8 x i32>, <8 x i32>* %A, align 8
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%S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%E = extractelement <8 x i32> %L, i32 %I
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ret void
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}
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@ -1,393 +0,0 @@
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; RUN: llc -mtriple=aarch64 -lower-interleaved-accesses=true < %s | FileCheck %s -check-prefix=NEON
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; RUN: llc -mtriple=aarch64 -lower-interleaved-accesses=true -mattr=-neon < %s | FileCheck %s -check-prefix=NONEON
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; NEON-LABEL: load_factor2:
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; NEON: ld2 { v0.8b, v1.8b }, [x0]
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; NONEON-LABEL: load_factor2:
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; NONEON-NOT: ld2
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define <8 x i8> @load_factor2(<16 x i8>* %ptr) {
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%wide.vec = load <16 x i8>, <16 x i8>* %ptr, align 4
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%strided.v0 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%strided.v1 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%add = add nsw <8 x i8> %strided.v0, %strided.v1
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ret <8 x i8> %add
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}
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; NEON-LABEL: load_factor3:
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; NEON: ld3 { v0.4s, v1.4s, v2.4s }, [x0]
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; NONEON-LABEL: load_factor3:
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; NONEON-NOT: ld3
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define <4 x i32> @load_factor3(i32* %ptr) {
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%base = bitcast i32* %ptr to <12 x i32>*
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%wide.vec = load <12 x i32>, <12 x i32>* %base, align 4
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%strided.v2 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
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%strided.v1 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
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%add = add nsw <4 x i32> %strided.v2, %strided.v1
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ret <4 x i32> %add
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}
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; NEON-LABEL: load_factor4:
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; NEON: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0]
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; NONEON-LABEL: load_factor4:
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; NONEON-NOT: ld4
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define <4 x i32> @load_factor4(i32* %ptr) {
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%base = bitcast i32* %ptr to <16 x i32>*
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%wide.vec = load <16 x i32>, <16 x i32>* %base, align 4
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%strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
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%strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
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%add = add nsw <4 x i32> %strided.v0, %strided.v2
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ret <4 x i32> %add
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}
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; NEON-LABEL: store_factor2:
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; NEON: st2 { v0.8b, v1.8b }, [x0]
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; NONEON-LABEL: store_factor2:
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; NONEON-NOT: st2
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define void @store_factor2(<16 x i8>* %ptr, <8 x i8> %v0, <8 x i8> %v1) {
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%interleaved.vec = shufflevector <8 x i8> %v0, <8 x i8> %v1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
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store <16 x i8> %interleaved.vec, <16 x i8>* %ptr, align 4
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ret void
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}
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; NEON-LABEL: store_factor3:
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; NEON: st3 { v0.4s, v1.4s, v2.4s }, [x0]
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; NONEON-LABEL: store_factor3:
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; NONEON-NOT: st3
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define void @store_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
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%base = bitcast i32* %ptr to <12 x i32>*
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%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%v2_u = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_u, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
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store <12 x i32> %interleaved.vec, <12 x i32>* %base, align 4
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ret void
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}
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; NEON-LABEL: store_factor4:
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; NEON: st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0]
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; NONEON-LABEL: store_factor4:
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; NONEON-NOT: st4
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define void @store_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
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%base = bitcast i32* %ptr to <16 x i32>*
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%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%v2_v3 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_v3, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
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store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4
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ret void
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}
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; The following cases test that interleaved access of pointer vectors can be
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; matched to ldN/stN instruction.
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; NEON-LABEL: load_ptrvec_factor2:
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; NEON: ld2 { v0.2d, v1.2d }, [x0]
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; NONEON-LABEL: load_ptrvec_factor2:
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; NONEON-NOT: ld2
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define <2 x i32*> @load_ptrvec_factor2(i32** %ptr) {
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%base = bitcast i32** %ptr to <4 x i32*>*
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%wide.vec = load <4 x i32*>, <4 x i32*>* %base, align 4
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%strided.v0 = shufflevector <4 x i32*> %wide.vec, <4 x i32*> undef, <2 x i32> <i32 0, i32 2>
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ret <2 x i32*> %strided.v0
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}
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; NEON-LABEL: load_ptrvec_factor3:
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; NEON: ld3 { v0.2d, v1.2d, v2.2d }, [x0]
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; NONEON-LABEL: load_ptrvec_factor3:
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; NONEON-NOT: ld3
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define void @load_ptrvec_factor3(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) {
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%base = bitcast i32** %ptr to <6 x i32*>*
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%wide.vec = load <6 x i32*>, <6 x i32*>* %base, align 4
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%strided.v2 = shufflevector <6 x i32*> %wide.vec, <6 x i32*> undef, <2 x i32> <i32 2, i32 5>
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store <2 x i32*> %strided.v2, <2 x i32*>* %ptr1
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%strided.v1 = shufflevector <6 x i32*> %wide.vec, <6 x i32*> undef, <2 x i32> <i32 1, i32 4>
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store <2 x i32*> %strided.v1, <2 x i32*>* %ptr2
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ret void
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}
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; NEON-LABEL: load_ptrvec_factor4:
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; NEON: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
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; NONEON-LABEL: load_ptrvec_factor4:
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; NONEON-NOT: ld4
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define void @load_ptrvec_factor4(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) {
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%base = bitcast i32** %ptr to <8 x i32*>*
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%wide.vec = load <8 x i32*>, <8 x i32*>* %base, align 4
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%strided.v1 = shufflevector <8 x i32*> %wide.vec, <8 x i32*> undef, <2 x i32> <i32 1, i32 5>
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%strided.v3 = shufflevector <8 x i32*> %wide.vec, <8 x i32*> undef, <2 x i32> <i32 3, i32 7>
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store <2 x i32*> %strided.v1, <2 x i32*>* %ptr1
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store <2 x i32*> %strided.v3, <2 x i32*>* %ptr2
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ret void
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}
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; NEON-LABEL: store_ptrvec_factor2:
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; NEON: st2 { v0.2d, v1.2d }, [x0]
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; NONEON-LABEL: store_ptrvec_factor2:
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; NONEON-NOT: st2
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define void @store_ptrvec_factor2(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1) {
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%base = bitcast i32** %ptr to <4 x i32*>*
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%interleaved.vec = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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store <4 x i32*> %interleaved.vec, <4 x i32*>* %base, align 4
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ret void
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}
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; NEON-LABEL: store_ptrvec_factor3:
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; NEON: st3 { v0.2d, v1.2d, v2.2d }, [x0]
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; NONEON-LABEL: store_ptrvec_factor3:
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; NONEON-NOT: st3
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define void @store_ptrvec_factor3(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2) {
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%base = bitcast i32** %ptr to <6 x i32*>*
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%v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%v2_u = shufflevector <2 x i32*> %v2, <2 x i32*> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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%interleaved.vec = shufflevector <4 x i32*> %v0_v1, <4 x i32*> %v2_u, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
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store <6 x i32*> %interleaved.vec, <6 x i32*>* %base, align 4
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ret void
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}
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; NEON-LABEL: store_ptrvec_factor4:
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; NEON: st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
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; NONEON-LABEL: store_ptrvec_factor4:
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; NONEON-NOT: st4
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define void @store_ptrvec_factor4(i32* %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2, <2 x i32*> %v3) {
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%base = bitcast i32* %ptr to <8 x i32*>*
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%v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%v2_v3 = shufflevector <2 x i32*> %v2, <2 x i32*> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%interleaved.vec = shufflevector <4 x i32*> %v0_v1, <4 x i32*> %v2_v3, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
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store <8 x i32*> %interleaved.vec, <8 x i32*>* %base, align 4
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ret void
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}
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; Following cases check that shuffle maskes with undef indices can be matched
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; into ldN/stN instruction.
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; NEON-LABEL: load_undef_mask_factor2:
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; NEON: ld2 { v0.4s, v1.4s }, [x0]
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; NONEON-LABEL: load_undef_mask_factor2:
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; NONEON-NOT: ld2
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define <4 x i32> @load_undef_mask_factor2(i32* %ptr) {
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%base = bitcast i32* %ptr to <8 x i32>*
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%wide.vec = load <8 x i32>, <8 x i32>* %base, align 4
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%strided.v0 = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 6>
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%strided.v1 = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 7>
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%add = add nsw <4 x i32> %strided.v0, %strided.v1
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ret <4 x i32> %add
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}
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; NEON-LABEL: load_undef_mask_factor3:
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; NEON: ld3 { v0.4s, v1.4s, v2.4s }, [x0]
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; NONEON-LABEL: load_undef_mask_factor3:
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; NONEON-NOT: ld3
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define <4 x i32> @load_undef_mask_factor3(i32* %ptr) {
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%base = bitcast i32* %ptr to <12 x i32>*
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%wide.vec = load <12 x i32>, <12 x i32>* %base, align 4
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%strided.v2 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef>
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%strided.v1 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
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%add = add nsw <4 x i32> %strided.v2, %strided.v1
|
||||
ret <4 x i32> %add
|
||||
}
|
||||
|
||||
; NEON-LABEL: load_undef_mask_factor4:
|
||||
; NEON: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0]
|
||||
; NONEON-LABEL: load_undef_mask_factor4:
|
||||
; NONEON-NOT: ld4
|
||||
define <4 x i32> @load_undef_mask_factor4(i32* %ptr) {
|
||||
%base = bitcast i32* %ptr to <16 x i32>*
|
||||
%wide.vec = load <16 x i32>, <16 x i32>* %base, align 4
|
||||
%strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 undef, i32 undef>
|
||||
%strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 undef, i32 undef>
|
||||
%add = add nsw <4 x i32> %strided.v0, %strided.v2
|
||||
ret <4 x i32> %add
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_undef_mask_factor2:
|
||||
; NEON: st2 { v0.4s, v1.4s }, [x0]
|
||||
; NONEON-LABEL: store_undef_mask_factor2:
|
||||
; NONEON-NOT: st2
|
||||
define void @store_undef_mask_factor2(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <8 x i32>*
|
||||
%interleaved.vec = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_undef_mask_factor3:
|
||||
; NEON: st3 { v0.4s, v1.4s, v2.4s }, [x0]
|
||||
; NONEON-LABEL: store_undef_mask_factor3:
|
||||
; NONEON-NOT: st3
|
||||
define void @store_undef_mask_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%v2_u = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_u, <12 x i32> <i32 0, i32 4, i32 undef, i32 1, i32 undef, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_undef_mask_factor4:
|
||||
; NEON: st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0]
|
||||
; NONEON-LABEL: store_undef_mask_factor4:
|
||||
; NONEON-NOT: st4
|
||||
define void @store_undef_mask_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
|
||||
%base = bitcast i32* %ptr to <16 x i32>*
|
||||
%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%v2_v3 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_v3, <16 x i32> <i32 0, i32 4, i32 8, i32 undef, i32 undef, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
|
||||
store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that we do something sane with illegal types.
|
||||
|
||||
; NEON-LABEL: load_illegal_factor2:
|
||||
; NEON: BB#0:
|
||||
; NEON-NEXT: ldr q[[V:[0-9]+]], [x0]
|
||||
; NEON-NEXT: uzp1 v0.4s, v[[V]].4s, v{{.*}}.4s
|
||||
; NEON-NEXT: ret
|
||||
; NONEON-LABEL: load_illegal_factor2:
|
||||
; NONEON: BB#0:
|
||||
; NONEON-NEXT: ldr s0, [x0]
|
||||
; NONEON-NEXT: ldr s1, [x0, #8]
|
||||
; NONEON-NEXT: ret
|
||||
define <3 x float> @load_illegal_factor2(<3 x float>* %p) nounwind {
|
||||
%tmp1 = load <3 x float>, <3 x float>* %p, align 16
|
||||
%tmp2 = shufflevector <3 x float> %tmp1, <3 x float> undef, <3 x i32> <i32 0, i32 2, i32 undef>
|
||||
ret <3 x float> %tmp2
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_illegal_factor2:
|
||||
; NEON: BB#0:
|
||||
; NEON-NEXT: uzp1 v0.4s, v0.4s, v{{.*}}.4s
|
||||
; NEON-NEXT: st1 { v0.d }[0], [x0]
|
||||
; NEON-NEXT: ret
|
||||
; NONEON-LABEL: store_illegal_factor2:
|
||||
; NONEON: BB#0:
|
||||
; NONEON-NEXT: fmov w[[ELT2:[0-9]+]], s2
|
||||
; NONEON-NEXT: fmov w[[RES:[0-9]+]], s0
|
||||
; NONEON-NEXT: bfi x[[RES]], x[[ELT2]], #32, #32
|
||||
; NONEON-NEXT: str x[[RES]], [x0]
|
||||
; NONEON-NEXT: ret
|
||||
define void @store_illegal_factor2(<3 x float>* %p, <3 x float> %v) nounwind {
|
||||
%tmp1 = shufflevector <3 x float> %v, <3 x float> undef, <3 x i32> <i32 0, i32 2, i32 undef>
|
||||
store <3 x float> %tmp1, <3 x float>* %p, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: load_factor2_with_extract_user:
|
||||
; NEON: ld2 { v0.4s, v1.4s }, [x0]
|
||||
; NEON: mov w0, v0.s[1]
|
||||
; NONEON-LABEL: load_factor2_with_extract_user:
|
||||
; NONEON-NOT: ld2
|
||||
define i32 @load_factor2_with_extract_user(<8 x i32>* %a) {
|
||||
%1 = load <8 x i32>, <8 x i32>* %a, align 8
|
||||
%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%3 = extractelement <8 x i32> %1, i32 2
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor4:
|
||||
; NEON: st4 { v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s }, [x0]
|
||||
; NONEON-LABEL: store_general_mask_factor4:
|
||||
; NONEON-NOT: st4
|
||||
define void @store_general_mask_factor4(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <8 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 16, i32 32, i32 8, i32 5, i32 17, i32 33, i32 9>
|
||||
store <8 x i32> %i.vec, <8 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor4_undefbeg:
|
||||
; NEON: st4 { v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s }, [x0]
|
||||
; NONEON-LABEL: store_general_mask_factor4_undefbeg:
|
||||
; NONEON-NOT: st4
|
||||
define void @store_general_mask_factor4_undefbeg(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <8 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 undef, i32 16, i32 32, i32 8, i32 5, i32 17, i32 33, i32 9>
|
||||
store <8 x i32> %i.vec, <8 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor4_undefend:
|
||||
; NEON: st4 { v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s }, [x0]
|
||||
; NONEON-LABEL: store_general_mask_factor4_undefend:
|
||||
; NONEON-NOT: st4
|
||||
define void @store_general_mask_factor4_undefend(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <8 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 16, i32 32, i32 8, i32 5, i32 17, i32 33, i32 undef>
|
||||
store <8 x i32> %i.vec, <8 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor4_undefmid:
|
||||
; NEON: st4 { v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s }, [x0]
|
||||
; NONEON-LABEL: store_general_mask_factor4_undefmid:
|
||||
; NONEON-NOT: st4
|
||||
define void @store_general_mask_factor4_undefmid(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <8 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 undef, i32 32, i32 8, i32 5, i32 17, i32 undef, i32 9>
|
||||
store <8 x i32> %i.vec, <8 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor4_undefmulti:
|
||||
; NEON: st4 { v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s }, [x0]
|
||||
; NONEON-LABEL: store_general_mask_factor4_undefmulti:
|
||||
; NONEON-NOT: st4
|
||||
define void @store_general_mask_factor4_undefmulti(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <8 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 undef, i32 undef, i32 8, i32 undef, i32 undef, i32 undef, i32 9>
|
||||
store <8 x i32> %i.vec, <8 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor3:
|
||||
; NEON: st3 { v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s }, [x0]
|
||||
; NONEON-LABEL: store_general_mask_factor3:
|
||||
; NONEON-NOT: st3
|
||||
define void @store_general_mask_factor3(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 4, i32 32, i32 16, i32 5, i32 33, i32 17, i32 6, i32 34, i32 18, i32 7, i32 35, i32 19>
|
||||
store <12 x i32> %i.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor3_undefmultimid:
|
||||
; NEON: st3 { v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s }, [x0]
|
||||
; NONEON-LABEL: store_general_mask_factor3_undefmultimid:
|
||||
; NONEON-NOT: st3
|
||||
define void @store_general_mask_factor3_undefmultimid(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 4, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 7, i32 35, i32 19>
|
||||
store <12 x i32> %i.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor3_undef_fail:
|
||||
; NEON-NOT: st3
|
||||
; NONEON-LABEL: store_general_mask_factor3_undef_fail:
|
||||
; NONEON-NOT: st3
|
||||
define void @store_general_mask_factor3_undef_fail(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 4, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 8, i32 35, i32 19>
|
||||
store <12 x i32> %i.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor3_undeflane:
|
||||
; NEON: st3 { v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s, v{{[0-9]+}}.{{[0-9]+}}s }, [x0]
|
||||
; NONEON-LABEL: store_general_mask_factor3_undeflane:
|
||||
; NONEON-NOT: st3
|
||||
define void @store_general_mask_factor3_undeflane(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 undef, i32 35, i32 19>
|
||||
store <12 x i32> %i.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor3_negativestart:
|
||||
; NEON-NOT: st3
|
||||
; NONEON-LABEL: store_general_mask_factor3_negativestart:
|
||||
; NONEON-NOT: st3
|
||||
define void @store_general_mask_factor3_negativestart(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 2, i32 35, i32 19>
|
||||
store <12 x i32> %i.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
|
|
@ -1,86 +0,0 @@
|
|||
; RUN: opt < %s -mtriple=arm-eabi -mattr=+neon -interleaved-access -S | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: @extract_user_basic(
|
||||
; CHECK: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
|
||||
; CHECK: %[[R:.+]] = extractvalue { <4 x i32>, <4 x i32> } %vldN, 0
|
||||
; CHECK: extractelement <4 x i32> %[[R]], i64 1
|
||||
define void @extract_user_basic(<8 x i32>* %A, i1 %C) {
|
||||
entry:
|
||||
%L = load <8 x i32>, <8 x i32>* %A, align 8
|
||||
%S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
br i1 %C, label %if.then, label %if.merge
|
||||
|
||||
if.then:
|
||||
%E = extractelement <8 x i32> %L, i32 2
|
||||
br label %if.merge
|
||||
|
||||
if.merge:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @extract_user_multi(
|
||||
; CHECK: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
|
||||
; CHECK: %[[R:.+]] = extractvalue { <4 x i32>, <4 x i32> } %vldN, 0
|
||||
; CHECK: extractelement <4 x i32> %[[R]], i64 0
|
||||
; CHECK: extractelement <4 x i32> %[[R]], i64 1
|
||||
define void @extract_user_multi(<8 x i32>* %A, i1 %C) {
|
||||
entry:
|
||||
%L = load <8 x i32>, <8 x i32>* %A, align 8
|
||||
%S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
br i1 %C, label %if.then, label %if.merge
|
||||
|
||||
if.then:
|
||||
%E1 = extractelement <8 x i32> %L, i32 0
|
||||
br label %if.merge
|
||||
|
||||
if.merge:
|
||||
%E2 = extractelement <8 x i32> %L, i32 2
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @extract_user_multi_no_dom(
|
||||
; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
|
||||
define void @extract_user_multi_no_dom(<8 x i32>* %A, i1 %C) {
|
||||
entry:
|
||||
%L = load <8 x i32>, <8 x i32>* %A, align 8
|
||||
%E1 = extractelement <8 x i32> %L, i32 0
|
||||
br i1 %C, label %if.then, label %if.merge
|
||||
|
||||
if.then:
|
||||
%S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%E2 = extractelement <8 x i32> %L, i32 2
|
||||
br label %if.merge
|
||||
|
||||
if.merge:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @extract_user_wrong_const_index(
|
||||
; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
|
||||
define void @extract_user_wrong_const_index(<8 x i32>* %A) {
|
||||
entry:
|
||||
%L = load <8 x i32>, <8 x i32>* %A, align 8
|
||||
%S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%E = extractelement <8 x i32> %L, i32 1
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @extract_user_undef_index(
|
||||
; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
|
||||
define void @extract_user_undef_index(<8 x i32>* %A) {
|
||||
entry:
|
||||
%L = load <8 x i32>, <8 x i32>* %A, align 8
|
||||
%S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%E = extractelement <8 x i32> %L, i32 undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @extract_user_var_index(
|
||||
; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
|
||||
define void @extract_user_var_index(<8 x i32>* %A, i32 %I) {
|
||||
entry:
|
||||
%L = load <8 x i32>, <8 x i32>* %A, align 8
|
||||
%S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%E = extractelement <8 x i32> %L, i32 %I
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1,462 +0,0 @@
|
|||
; RUN: llc -mtriple=arm-eabi -mattr=+neon -lower-interleaved-accesses=true < %s | FileCheck %s -check-prefix=NEON
|
||||
; RUN: llc -mtriple=arm-eabi -mattr=-neon -lower-interleaved-accesses=true < %s | FileCheck %s -check-prefix=NONEON
|
||||
|
||||
; NEON-LABEL: load_factor2:
|
||||
; NEON: vld2.8 {d16, d17}, [r0]
|
||||
; NONEON-LABEL: load_factor2:
|
||||
; NONEON-NOT: vld2
|
||||
define <8 x i8> @load_factor2(<16 x i8>* %ptr) {
|
||||
%wide.vec = load <16 x i8>, <16 x i8>* %ptr, align 4
|
||||
%strided.v0 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
|
||||
%strided.v1 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
|
||||
%add = add nsw <8 x i8> %strided.v0, %strided.v1
|
||||
ret <8 x i8> %add
|
||||
}
|
||||
|
||||
; NEON-LABEL: load_factor3:
|
||||
; NEON: vld3.32 {d16, d17, d18}, [r0]
|
||||
; NONEON-LABEL: load_factor3:
|
||||
; NONEON-NOT: vld3
|
||||
define <2 x i32> @load_factor3(i32* %ptr) {
|
||||
%base = bitcast i32* %ptr to <6 x i32>*
|
||||
%wide.vec = load <6 x i32>, <6 x i32>* %base, align 4
|
||||
%strided.v2 = shufflevector <6 x i32> %wide.vec, <6 x i32> undef, <2 x i32> <i32 2, i32 5>
|
||||
%strided.v1 = shufflevector <6 x i32> %wide.vec, <6 x i32> undef, <2 x i32> <i32 1, i32 4>
|
||||
%add = add nsw <2 x i32> %strided.v2, %strided.v1
|
||||
ret <2 x i32> %add
|
||||
}
|
||||
|
||||
; NEON-LABEL: load_factor4:
|
||||
; NEON: vld4.32 {d16, d18, d20, d22}, [r0]!
|
||||
; NEON: vld4.32 {d17, d19, d21, d23}, [r0]
|
||||
; NONEON-LABEL: load_factor4:
|
||||
; NONEON-NOT: vld4
|
||||
define <4 x i32> @load_factor4(i32* %ptr) {
|
||||
%base = bitcast i32* %ptr to <16 x i32>*
|
||||
%wide.vec = load <16 x i32>, <16 x i32>* %base, align 4
|
||||
%strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
|
||||
%strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
|
||||
%add = add nsw <4 x i32> %strided.v0, %strided.v2
|
||||
ret <4 x i32> %add
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_factor2:
|
||||
; NEON: vst2.8 {d16, d17}, [r0]
|
||||
; NONEON-LABEL: store_factor2:
|
||||
; NONEON-NOT: vst2
|
||||
define void @store_factor2(<16 x i8>* %ptr, <8 x i8> %v0, <8 x i8> %v1) {
|
||||
%interleaved.vec = shufflevector <8 x i8> %v0, <8 x i8> %v1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
|
||||
store <16 x i8> %interleaved.vec, <16 x i8>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_factor3:
|
||||
; NEON: vst3.32 {d16, d18, d20}, [r0]!
|
||||
; NEON: vst3.32 {d17, d19, d21}, [r0]
|
||||
; NONEON-LABEL: store_factor3:
|
||||
; NONEON-NOT: vst3.32
|
||||
define void @store_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%v2_u = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_u, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_factor4:
|
||||
; NEON: vst4.32 {d16, d18, d20, d22}, [r0]!
|
||||
; NEON: vst4.32 {d17, d19, d21, d23}, [r0]
|
||||
; NONEON-LABEL: store_factor4:
|
||||
; NONEON-NOT: vst4
|
||||
define void @store_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
|
||||
%base = bitcast i32* %ptr to <16 x i32>*
|
||||
%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%v2_v3 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_v3, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
|
||||
store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; The following cases test that interleaved access of pointer vectors can be
|
||||
; matched to ldN/stN instruction.
|
||||
|
||||
; NEON-LABEL: load_ptrvec_factor2:
|
||||
; NEON: vld2.32 {d16, d17}, [r0]
|
||||
; NONEON-LABEL: load_ptrvec_factor2:
|
||||
; NONEON-NOT: vld2
|
||||
define <2 x i32*> @load_ptrvec_factor2(i32** %ptr) {
|
||||
%base = bitcast i32** %ptr to <4 x i32*>*
|
||||
%wide.vec = load <4 x i32*>, <4 x i32*>* %base, align 4
|
||||
%strided.v0 = shufflevector <4 x i32*> %wide.vec, <4 x i32*> undef, <2 x i32> <i32 0, i32 2>
|
||||
ret <2 x i32*> %strided.v0
|
||||
}
|
||||
|
||||
; NEON-LABEL: load_ptrvec_factor3:
|
||||
; NEON: vld3.32 {d16, d17, d18}, [r0]
|
||||
; NONEON-LABEL: load_ptrvec_factor3:
|
||||
; NONEON-NOT: vld3
|
||||
define void @load_ptrvec_factor3(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) {
|
||||
%base = bitcast i32** %ptr to <6 x i32*>*
|
||||
%wide.vec = load <6 x i32*>, <6 x i32*>* %base, align 4
|
||||
%strided.v2 = shufflevector <6 x i32*> %wide.vec, <6 x i32*> undef, <2 x i32> <i32 2, i32 5>
|
||||
store <2 x i32*> %strided.v2, <2 x i32*>* %ptr1
|
||||
%strided.v1 = shufflevector <6 x i32*> %wide.vec, <6 x i32*> undef, <2 x i32> <i32 1, i32 4>
|
||||
store <2 x i32*> %strided.v1, <2 x i32*>* %ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: load_ptrvec_factor4:
|
||||
; NEON: vld4.32 {d16, d17, d18, d19}, [r0]
|
||||
; NONEON-LABEL: load_ptrvec_factor4:
|
||||
; NONEON-NOT: vld4
|
||||
define void @load_ptrvec_factor4(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) {
|
||||
%base = bitcast i32** %ptr to <8 x i32*>*
|
||||
%wide.vec = load <8 x i32*>, <8 x i32*>* %base, align 4
|
||||
%strided.v1 = shufflevector <8 x i32*> %wide.vec, <8 x i32*> undef, <2 x i32> <i32 1, i32 5>
|
||||
%strided.v3 = shufflevector <8 x i32*> %wide.vec, <8 x i32*> undef, <2 x i32> <i32 3, i32 7>
|
||||
store <2 x i32*> %strided.v1, <2 x i32*>* %ptr1
|
||||
store <2 x i32*> %strided.v3, <2 x i32*>* %ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_ptrvec_factor2:
|
||||
; NEON: vst2.32 {d16, d17}, [r0]
|
||||
; NONEON-LABEL: store_ptrvec_factor2:
|
||||
; NONEON-NOT: vst2
|
||||
define void @store_ptrvec_factor2(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1) {
|
||||
%base = bitcast i32** %ptr to <4 x i32*>*
|
||||
%interleaved.vec = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
||||
store <4 x i32*> %interleaved.vec, <4 x i32*>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_ptrvec_factor3:
|
||||
; NEON: vst3.32 {d16, d17, d18}, [r0]
|
||||
; NONEON-LABEL: store_ptrvec_factor3:
|
||||
; NONEON-NOT: vst3
|
||||
define void @store_ptrvec_factor3(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2) {
|
||||
%base = bitcast i32** %ptr to <6 x i32*>*
|
||||
%v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%v2_u = shufflevector <2 x i32*> %v2, <2 x i32*> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
|
||||
%interleaved.vec = shufflevector <4 x i32*> %v0_v1, <4 x i32*> %v2_u, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
|
||||
store <6 x i32*> %interleaved.vec, <6 x i32*>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_ptrvec_factor4:
|
||||
; NEON: vst4.32 {d16, d17, d18, d19}, [r0]
|
||||
; NONEON-LABEL: store_ptrvec_factor4:
|
||||
; NONEON-NOT: vst4
|
||||
define void @store_ptrvec_factor4(i32* %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2, <2 x i32*> %v3) {
|
||||
%base = bitcast i32* %ptr to <8 x i32*>*
|
||||
%v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%v2_v3 = shufflevector <2 x i32*> %v2, <2 x i32*> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%interleaved.vec = shufflevector <4 x i32*> %v0_v1, <4 x i32*> %v2_v3, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
|
||||
store <8 x i32*> %interleaved.vec, <8 x i32*>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Following cases check that shuffle maskes with undef indices can be matched
|
||||
; into ldN/stN instruction.
|
||||
|
||||
; NEON-LABEL: load_undef_mask_factor2:
|
||||
; NEON: vld2.32 {d16, d17, d18, d19}, [r0]
|
||||
; NONEON-LABEL: load_undef_mask_factor2:
|
||||
; NONEON-NOT: vld2
|
||||
define <4 x i32> @load_undef_mask_factor2(i32* %ptr) {
|
||||
%base = bitcast i32* %ptr to <8 x i32>*
|
||||
%wide.vec = load <8 x i32>, <8 x i32>* %base, align 4
|
||||
%strided.v0 = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 6>
|
||||
%strided.v1 = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 7>
|
||||
%add = add nsw <4 x i32> %strided.v0, %strided.v1
|
||||
ret <4 x i32> %add
|
||||
}
|
||||
|
||||
; NEON-LABEL: load_undef_mask_factor3:
|
||||
; NEON: vld3.32 {d16, d18, d20}, [r0]!
|
||||
; NEON: vld3.32 {d17, d19, d21}, [r0]
|
||||
; NONEON-LABEL: load_undef_mask_factor3:
|
||||
; NONEON-NOT: vld3
|
||||
define <4 x i32> @load_undef_mask_factor3(i32* %ptr) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%wide.vec = load <12 x i32>, <12 x i32>* %base, align 4
|
||||
%strided.v2 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef>
|
||||
%strided.v1 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
|
||||
%add = add nsw <4 x i32> %strided.v2, %strided.v1
|
||||
ret <4 x i32> %add
|
||||
}
|
||||
|
||||
; NEON-LABEL: load_undef_mask_factor4:
|
||||
; NEON: vld4.32 {d16, d18, d20, d22}, [r0]!
|
||||
; NEON: vld4.32 {d17, d19, d21, d23}, [r0]
|
||||
; NONEON-LABEL: load_undef_mask_factor4:
|
||||
; NONEON-NOT: vld4
|
||||
define <4 x i32> @load_undef_mask_factor4(i32* %ptr) {
|
||||
%base = bitcast i32* %ptr to <16 x i32>*
|
||||
%wide.vec = load <16 x i32>, <16 x i32>* %base, align 4
|
||||
%strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 undef, i32 undef>
|
||||
%strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 undef, i32 undef>
|
||||
%add = add nsw <4 x i32> %strided.v0, %strided.v2
|
||||
ret <4 x i32> %add
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_undef_mask_factor2:
|
||||
; NEON: vst2.32 {d16, d17, d18, d19}, [r0]
|
||||
; NONEON-LABEL: store_undef_mask_factor2:
|
||||
; NONEON-NOT: vst2
|
||||
define void @store_undef_mask_factor2(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <8 x i32>*
|
||||
%interleaved.vec = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_undef_mask_factor3:
|
||||
; NEON: vst3.32 {d16, d18, d20}, [r0]!
|
||||
; NEON: vst3.32 {d17, d19, d21}, [r0]
|
||||
; NONEON-LABEL: store_undef_mask_factor3:
|
||||
; NONEON-NOT: vst3
|
||||
define void @store_undef_mask_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%v2_u = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_u, <12 x i32> <i32 0, i32 4, i32 undef, i32 1, i32 undef, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_undef_mask_factor4:
|
||||
; NEON: vst4.32 {d16, d18, d20, d22}, [r0]!
|
||||
; NEON: vst4.32 {d17, d19, d21, d23}, [r0]
|
||||
; NONEON-LABEL: store_undef_mask_factor4:
|
||||
; NONEON-NOT: vst4
|
||||
define void @store_undef_mask_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
|
||||
%base = bitcast i32* %ptr to <16 x i32>*
|
||||
%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%v2_v3 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_v3, <16 x i32> <i32 0, i32 4, i32 8, i32 undef, i32 undef, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
|
||||
store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; The following test cases check that address spaces are properly handled
|
||||
|
||||
; NEON-LABEL: load_address_space
|
||||
; NEON: vld3.32
|
||||
; NONEON-LABEL: load_address_space
|
||||
; NONEON-NOT: vld3
|
||||
define void @load_address_space(<4 x i32> addrspace(1)* %A, <2 x i32>* %B) {
|
||||
%tmp = load <4 x i32>, <4 x i32> addrspace(1)* %A
|
||||
%interleaved = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 0, i32 3>
|
||||
store <2 x i32> %interleaved, <2 x i32>* %B
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_address_space
|
||||
; NEON: vst2.32
|
||||
; NONEON-LABEL: store_address_space
|
||||
; NONEON-NOT: vst2
|
||||
define void @store_address_space(<2 x i32>* %A, <2 x i32>* %B, <4 x i32> addrspace(1)* %C) {
|
||||
%tmp0 = load <2 x i32>, <2 x i32>* %A
|
||||
%tmp1 = load <2 x i32>, <2 x i32>* %B
|
||||
%interleaved = shufflevector <2 x i32> %tmp0, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
||||
store <4 x i32> %interleaved, <4 x i32> addrspace(1)* %C
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that we do something sane with illegal types.
|
||||
|
||||
; NEON-LABEL: load_illegal_factor2:
|
||||
; NEON: BB#0:
|
||||
; NEON-NEXT: vld1.64 {d16, d17}, [r0:128]
|
||||
; NEON-NEXT: vuzp.32 q8, {{.*}}
|
||||
; NEON-NEXT: vmov r0, r1, d16
|
||||
; NEON-NEXT: vmov r2, r3, {{.*}}
|
||||
; NEON-NEXT: mov pc, lr
|
||||
; NONEON-LABEL: load_illegal_factor2:
|
||||
; NONEON: BB#0:
|
||||
; NONEON-NEXT: ldr [[ELT0:r[0-9]+]], [r0]
|
||||
; NONEON-NEXT: ldr r1, [r0, #8]
|
||||
; NONEON-NEXT: mov r0, [[ELT0]]
|
||||
; NONEON-NEXT: mov pc, lr
|
||||
define <3 x float> @load_illegal_factor2(<3 x float>* %p) nounwind {
|
||||
%tmp1 = load <3 x float>, <3 x float>* %p, align 16
|
||||
%tmp2 = shufflevector <3 x float> %tmp1, <3 x float> undef, <3 x i32> <i32 0, i32 2, i32 undef>
|
||||
ret <3 x float> %tmp2
|
||||
}
|
||||
|
||||
; This lowering isn't great, but it's at least correct.
|
||||
|
||||
; NEON-LABEL: store_illegal_factor2:
|
||||
; NEON: BB#0:
|
||||
; NEON-NEXT: vldr d17, [sp]
|
||||
; NEON-NEXT: vmov d16, r2, r3
|
||||
; NEON-NEXT: vuzp.32 q8, {{.*}}
|
||||
; NEON-NEXT: vstr d16, [r0]
|
||||
; NEON-NEXT: mov pc, lr
|
||||
; NONEON-LABEL: store_illegal_factor2:
|
||||
; NONEON: BB#0:
|
||||
; NONEON-NEXT: stm r0, {r1, r3}
|
||||
; NONEON-NEXT: mov pc, lr
|
||||
define void @store_illegal_factor2(<3 x float>* %p, <3 x float> %v) nounwind {
|
||||
%tmp1 = shufflevector <3 x float> %v, <3 x float> undef, <3 x i32> <i32 0, i32 2, i32 undef>
|
||||
store <3 x float> %tmp1, <3 x float>* %p, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: load_factor2_with_extract_user:
|
||||
; NEON: vld2.32 {d16, d17, d18, d19}, [r0:64]
|
||||
; NEON: vmov.32 r0, d16[1]
|
||||
; NONEON-LABEL: load_factor2_with_extract_user:
|
||||
; NONEON-NOT: vld2
|
||||
define i32 @load_factor2_with_extract_user(<8 x i32>* %a) {
|
||||
%1 = load <8 x i32>, <8 x i32>* %a, align 8
|
||||
%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%3 = extractelement <8 x i32> %1, i32 2
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor4:
|
||||
; NEON: vst4.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
|
||||
; NONEON-LABEL: store_general_mask_factor4:
|
||||
; NONEON-NOT: vst4.32
|
||||
define void @store_general_mask_factor4(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <8 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 16, i32 32, i32 8, i32 5, i32 17, i32 33, i32 9>
|
||||
store <8 x i32> %i.vec, <8 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor4_undefbeg:
|
||||
; NEON: vst4.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
|
||||
; NONEON-LABEL: store_general_mask_factor4_undefbeg:
|
||||
; NONEON-NOT: vst4.32
|
||||
define void @store_general_mask_factor4_undefbeg(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <8 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 undef, i32 16, i32 32, i32 8, i32 5, i32 17, i32 33, i32 9>
|
||||
store <8 x i32> %i.vec, <8 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor4_undefend:
|
||||
; NEON: vst4.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
|
||||
; NONEON-LABEL: store_general_mask_factor4_undefend:
|
||||
; NONEON-NOT: vst4.32
|
||||
define void @store_general_mask_factor4_undefend(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <8 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 16, i32 32, i32 8, i32 5, i32 17, i32 33, i32 undef>
|
||||
store <8 x i32> %i.vec, <8 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor4_undefmid:
|
||||
; NEON: vst4.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
|
||||
; NONEON-LABEL: store_general_mask_factor4_undefmid:
|
||||
; NONEON-NOT: vst4.32
|
||||
define void @store_general_mask_factor4_undefmid(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <8 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 undef, i32 32, i32 8, i32 5, i32 17, i32 undef, i32 9>
|
||||
store <8 x i32> %i.vec, <8 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor4_undefmulti:
|
||||
; NEON: vst4.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
|
||||
; NONEON-LABEL: store_general_mask_factor4_undefmulti:
|
||||
; NONEON-NOT: vst4.32
|
||||
define void @store_general_mask_factor4_undefmulti(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <8 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 undef, i32 undef, i32 8, i32 undef, i32 undef, i32 undef, i32 9>
|
||||
store <8 x i32> %i.vec, <8 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor3:
|
||||
; NEON: vst3.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
|
||||
; NONEON-LABEL: store_general_mask_factor3:
|
||||
; NONEON-NOT: vst3.32
|
||||
define void @store_general_mask_factor3(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 4, i32 32, i32 16, i32 5, i32 33, i32 17, i32 6, i32 34, i32 18, i32 7, i32 35, i32 19>
|
||||
store <12 x i32> %i.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor3_undefmultimid:
|
||||
; NEON: vst3.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
|
||||
; NONEON-LABEL: store_general_mask_factor3_undefmultimid:
|
||||
; NONEON-NOT: vst3.32
|
||||
define void @store_general_mask_factor3_undefmultimid(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 4, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 7, i32 35, i32 19>
|
||||
store <12 x i32> %i.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor3_undef_fail:
|
||||
; NEON-NOT: vst3.32
|
||||
; NONEON-LABEL: store_general_mask_factor3_undef_fail:
|
||||
; NONEON-NOT: vst3.32
|
||||
define void @store_general_mask_factor3_undef_fail(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 4, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 8, i32 35, i32 19>
|
||||
store <12 x i32> %i.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor3_undeflane:
|
||||
; NEON: vst3.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
|
||||
; NONEON-LABEL: store_general_mask_factor3_undeflane:
|
||||
; NONEON-NOT: vst3.32
|
||||
define void @store_general_mask_factor3_undeflane(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 undef, i32 35, i32 19>
|
||||
store <12 x i32> %i.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor3_endstart_fail:
|
||||
; NEON-NOT: vst3.32
|
||||
; NONEON-LABEL: store_general_mask_factor3_endstart_fail:
|
||||
; NONEON-NOT: vst3.32
|
||||
define void @store_general_mask_factor3_endstart_fail(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 2, i32 35, i32 19>
|
||||
store <12 x i32> %i.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor3_endstart_pass:
|
||||
; NEON: vst3.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
|
||||
; NONEON-LABEL: store_general_mask_factor3_endstart_pass:
|
||||
; NONEON-NOT: vst3.32
|
||||
define void @store_general_mask_factor3_endstart_pass(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 7, i32 35, i32 19>
|
||||
store <12 x i32> %i.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor3_midstart_fail:
|
||||
; NEON-NOT: vst3.32
|
||||
; NONEON-LABEL: store_general_mask_factor3_midstart_fail:
|
||||
; NONEON-NOT: vst3.32
|
||||
define void @store_general_mask_factor3_midstart_fail(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 0, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 undef, i32 35, i32 19>
|
||||
store <12 x i32> %i.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON-LABEL: store_general_mask_factor3_midstart_pass:
|
||||
; NEON: vst3.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
|
||||
; NONEON-LABEL: store_general_mask_factor3_midstart_pass:
|
||||
; NONEON-NOT: vst3.32
|
||||
define void @store_general_mask_factor3_midstart_pass(i32* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
%base = bitcast i32* %ptr to <12 x i32>*
|
||||
%i.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 1, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 undef, i32 35, i32 19>
|
||||
store <12 x i32> %i.vec, <12 x i32>* %base, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
; RUN: opt < %s -interleaved-access -S | FileCheck %s
|
||||
|
||||
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
|
||||
target triple = "aarch64--linux-gnu"
|
||||
|
||||
define void @extract_user_basic(<8 x i32>* %ptr, i1 %c) {
|
||||
; CHECK-LABEL: @extract_user_basic(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i32>* %ptr to <4 x i32>*
|
||||
; CHECK-NEXT: [[LDN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32(<4 x i32>* [[TMP0]])
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[LDN]], 0
|
||||
; CHECK-NEXT: br i1 %c, label %if.then, label %if.merge
|
||||
; CHECK: if.then:
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
|
||||
; CHECK-NEXT: br label %if.merge
|
||||
; CHECK: if.merge:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 8
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
br i1 %c, label %if.then, label %if.merge
|
||||
|
||||
if.then:
|
||||
%e0 = extractelement <8 x i32> %interleaved.vec, i32 2
|
||||
br label %if.merge
|
||||
|
||||
if.merge:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @extract_user_multi(<8 x i32>* %ptr, i1 %c) {
|
||||
; CHECK-LABEL: @extract_user_multi(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i32>* %ptr to <4 x i32>*
|
||||
; CHECK-NEXT: [[LDN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32(<4 x i32>* [[TMP0]])
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[LDN]], 0
|
||||
; CHECK-NEXT: br i1 %c, label %if.then, label %if.merge
|
||||
; CHECK: if.then:
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
|
||||
; CHECK-NEXT: br label %if.merge
|
||||
; CHECK: if.merge:
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 8
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
br i1 %c, label %if.then, label %if.merge
|
||||
|
||||
if.then:
|
||||
%e0 = extractelement <8 x i32> %interleaved.vec, i32 0
|
||||
br label %if.merge
|
||||
|
||||
if.merge:
|
||||
%e1 = extractelement <8 x i32> %interleaved.vec, i32 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @extract_user_multi_no_dom(<8 x i32>* %ptr, i1 %c) {
|
||||
; CHECK-LABEL: @extract_user_multi_no_dom(
|
||||
; CHECK-NOT: @llvm.aarch64.neon
|
||||
; CHECK: ret void
|
||||
;
|
||||
entry:
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 8
|
||||
%e0 = extractelement <8 x i32> %interleaved.vec, i32 0
|
||||
br i1 %c, label %if.then, label %if.merge
|
||||
|
||||
if.then:
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%e1 = extractelement <8 x i32> %interleaved.vec, i32 2
|
||||
br label %if.merge
|
||||
|
||||
if.merge:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @extract_user_wrong_const_index(<8 x i32>* %ptr) {
|
||||
; CHECK-LABEL: @extract_user_wrong_const_index(
|
||||
; CHECK-NOT: @llvm.aarch64.neon
|
||||
; CHECK: ret void
|
||||
;
|
||||
entry:
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 8
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%e0 = extractelement <8 x i32> %interleaved.vec, i32 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @extract_user_undef_index(<8 x i32>* %ptr) {
|
||||
; CHECK-LABEL: @extract_user_undef_index(
|
||||
; CHECK-NOT: @llvm.aarch64.neon
|
||||
; CHECK: ret void
|
||||
;
|
||||
entry:
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 8
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%e0 = extractelement <8 x i32> %interleaved.vec, i32 undef
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @extract_user_var_index(<8 x i32>* %ptr, i32 %i) {
|
||||
; CHECK-LABEL: @extract_user_var_index(
|
||||
; CHECK-NOT: @llvm.aarch64.neon
|
||||
; CHECK: ret void
|
||||
;
|
||||
entry:
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 8
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%e0 = extractelement <8 x i32> %interleaved.vec, i32 %i
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,549 @@
|
|||
; RUN: opt < %s -interleaved-access -S | FileCheck %s -check-prefix=NEON
|
||||
; RUN: opt < %s -mattr=-neon -interleaved-access -S | FileCheck %s -check-prefix=NO_NEON
|
||||
|
||||
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
|
||||
target triple = "aarch64--linux-gnu"
|
||||
|
||||
define void @load_factor2(<16 x i8>* %ptr) {
|
||||
; NEON-LABEL: @load_factor2(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <16 x i8>* %ptr to <8 x i8>*
|
||||
; NEON-NEXT: [[LDN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 x i8>* [[TMP1]])
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[LDN]], 1
|
||||
; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[LDN]], 0
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_factor2(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <16 x i8>, <16 x i8>* %ptr, align 4
|
||||
%v0 = shufflevector <16 x i8> %interleaved.vec, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
|
||||
%v1 = shufflevector <16 x i8> %interleaved.vec, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_factor3(<12 x i32>* %ptr) {
|
||||
; NEON-LABEL: @load_factor3(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <12 x i32>* %ptr to <4 x i32>*
|
||||
; NEON-NEXT: [[LDN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0v4i32(<4 x i32>* [[TMP1]])
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 2
|
||||
; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 1
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 0
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_factor3(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <12 x i32>, <12 x i32>* %ptr, align 4
|
||||
%v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
|
||||
%v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
|
||||
%v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_factor4(<16 x i32>* %ptr) {
|
||||
; NEON-LABEL: @load_factor4(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <16 x i32>* %ptr to <4 x i32>*
|
||||
; NEON-NEXT: [[LDN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4.v4i32.p0v4i32(<4 x i32>* [[TMP1]])
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 3
|
||||
; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 2
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 1
|
||||
; NEON-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 0
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_factor4(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <16 x i32>, <16 x i32>* %ptr, align 4
|
||||
%v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
|
||||
%v1 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
|
||||
%v2 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
|
||||
%v3 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_factor2(<16 x i8>* %ptr, <8 x i8> %v0, <8 x i8> %v1) {
|
||||
; NEON-LABEL: @store_factor2(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = bitcast <16 x i8>* %ptr to <8 x i8>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st2.v8i8.p0v8i8(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]], <8 x i8>* [[TMP3]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_factor2(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <8 x i8> %v0, <8 x i8> %v1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
|
||||
store <16 x i8> %interleaved.vec, <16 x i8>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_factor3(<12 x i32>* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
|
||||
; NEON-LABEL: @store_factor3(
|
||||
; NEON: [[TMP1:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = bitcast <12 x i32>* %ptr to <4 x i32>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st3.v4i32.p0v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32>* [[TMP4]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_factor3(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%s1 = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
%interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_factor4(<16 x i32>* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
|
||||
; NEON-LABEL: @store_factor4(
|
||||
; NEON: [[TMP1:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = bitcast <16 x i32>* %ptr to <4 x i32>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st4.v4i32.p0v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32>* [[TMP5]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_factor4(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%s1 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
|
||||
store <16 x i32> %interleaved.vec, <16 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_ptrvec_factor2(<4 x i32*>* %ptr) {
|
||||
; NEON-LABEL: @load_ptrvec_factor2(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <4 x i32*>* %ptr to <2 x i64>*
|
||||
; NEON-NEXT: [[LDN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2.v2i64.p0v2i64(<2 x i64>* [[TMP1]])
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[LDN]], 1
|
||||
; NEON-NEXT: [[TMP3:%.*]] = inttoptr <2 x i64> [[TMP2]] to <2 x i32*>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[LDN]], 0
|
||||
; NEON-NEXT: [[TMP5:%.*]] = inttoptr <2 x i64> [[TMP4]] to <2 x i32*>
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_ptrvec_factor2(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <4 x i32*>, <4 x i32*>* %ptr, align 4
|
||||
%v0 = shufflevector <4 x i32*> %interleaved.vec, <4 x i32*> undef, <2 x i32> <i32 0, i32 2>
|
||||
%v1 = shufflevector <4 x i32*> %interleaved.vec, <4 x i32*> undef, <2 x i32> <i32 1, i32 3>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_ptrvec_factor3(<6 x i32*>* %ptr) {
|
||||
; NEON-LABEL: @load_ptrvec_factor3(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <6 x i32*>* %ptr to <2 x i64>*
|
||||
; NEON-NEXT: [[LDN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3.v2i64.p0v2i64(<2 x i64>* [[TMP1]])
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64> } [[LDN]], 2
|
||||
; NEON-NEXT: [[TMP3:%.*]] = inttoptr <2 x i64> [[TMP2]] to <2 x i32*>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64> } [[LDN]], 1
|
||||
; NEON-NEXT: [[TMP5:%.*]] = inttoptr <2 x i64> [[TMP4]] to <2 x i32*>
|
||||
; NEON-NEXT: [[TMP6:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64> } [[LDN]], 0
|
||||
; NEON-NEXT: [[TMP7:%.*]] = inttoptr <2 x i64> [[TMP6]] to <2 x i32*>
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_ptrvec_factor3(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <6 x i32*>, <6 x i32*>* %ptr, align 4
|
||||
%v0 = shufflevector <6 x i32*> %interleaved.vec, <6 x i32*> undef, <2 x i32> <i32 0, i32 3>
|
||||
%v1 = shufflevector <6 x i32*> %interleaved.vec, <6 x i32*> undef, <2 x i32> <i32 1, i32 4>
|
||||
%v2 = shufflevector <6 x i32*> %interleaved.vec, <6 x i32*> undef, <2 x i32> <i32 2, i32 5>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_ptrvec_factor4(<8 x i32*>* %ptr) {
|
||||
; NEON-LABEL: @load_ptrvec_factor4(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <8 x i32*>* %ptr to <2 x i64>*
|
||||
; NEON-NEXT: [[LDN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0v2i64(<2 x i64>* [[TMP1]])
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[LDN]], 3
|
||||
; NEON-NEXT: [[TMP3:%.*]] = inttoptr <2 x i64> [[TMP2]] to <2 x i32*>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[LDN]], 2
|
||||
; NEON-NEXT: [[TMP5:%.*]] = inttoptr <2 x i64> [[TMP4]] to <2 x i32*>
|
||||
; NEON-NEXT: [[TMP6:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[LDN]], 1
|
||||
; NEON-NEXT: [[TMP7:%.*]] = inttoptr <2 x i64> [[TMP6]] to <2 x i32*>
|
||||
; NEON-NEXT: [[TMP8:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[LDN]], 0
|
||||
; NEON-NEXT: [[TMP9:%.*]] = inttoptr <2 x i64> [[TMP8]] to <2 x i32*>
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_ptrvec_factor4(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <8 x i32*>, <8 x i32*>* %ptr, align 4
|
||||
%v0 = shufflevector <8 x i32*> %interleaved.vec, <8 x i32*> undef, <2 x i32> <i32 0, i32 4>
|
||||
%v1 = shufflevector <8 x i32*> %interleaved.vec, <8 x i32*> undef, <2 x i32> <i32 1, i32 5>
|
||||
%v2 = shufflevector <8 x i32*> %interleaved.vec, <8 x i32*> undef, <2 x i32> <i32 2, i32 6>
|
||||
%v3 = shufflevector <8 x i32*> %interleaved.vec, <8 x i32*> undef, <2 x i32> <i32 3, i32 7>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_ptrvec_factor2(<4 x i32*>* %ptr, <2 x i32*> %v0, <2 x i32*> %v1) {
|
||||
; NEON-LABEL: @store_ptrvec_factor2(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = ptrtoint <2 x i32*> %v0 to <2 x i64>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = ptrtoint <2 x i32*> %v1 to <2 x i64>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP2]], <2 x i32> <i32 0, i32 1>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP2]], <2 x i32> <i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = bitcast <4 x i32*>* %ptr to <2 x i64>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st2.v2i64.p0v2i64(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i64>* [[TMP5]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_ptrvec_factor2(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
||||
store <4 x i32*> %interleaved.vec, <4 x i32*>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_ptrvec_factor3(<6 x i32*>* %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2) {
|
||||
; NEON-LABEL: @store_ptrvec_factor3(
|
||||
; NEON: [[TMP1:%.*]] = ptrtoint <4 x i32*> %s0 to <4 x i64>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = ptrtoint <4 x i32*> %s1 to <4 x i64>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP2]], <2 x i32> <i32 0, i32 1>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP2]], <2 x i32> <i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP2]], <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: [[TMP6:%.*]] = bitcast <6 x i32*>* %ptr to <2 x i64>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st3.v2i64.p0v2i64(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]], <2 x i64>* [[TMP6]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_ptrvec_factor3(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%s0 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%s1 = shufflevector <2 x i32*> %v2, <2 x i32*> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
|
||||
%interleaved.vec = shufflevector <4 x i32*> %s0, <4 x i32*> %s1, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
|
||||
store <6 x i32*> %interleaved.vec, <6 x i32*>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_ptrvec_factor4(<8 x i32*>* %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2, <2 x i32*> %v3) {
|
||||
; NEON-LABEL: @store_ptrvec_factor4(
|
||||
; NEON: [[TMP1:%.*]] = ptrtoint <4 x i32*> %s0 to <4 x i64>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = ptrtoint <4 x i32*> %s1 to <4 x i64>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP2]], <2 x i32> <i32 0, i32 1>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP2]], <2 x i32> <i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP2]], <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: [[TMP6:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP2]], <2 x i32> <i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP7:%.*]] = bitcast <8 x i32*>* %ptr to <2 x i64>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st4.v2i64.p0v2i64(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]], <2 x i64> [[TMP6]], <2 x i64>* [[TMP7]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_ptrvec_factor4(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%s0 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%s1 = shufflevector <2 x i32*> %v2, <2 x i32*> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%interleaved.vec = shufflevector <4 x i32*> %s0, <4 x i32*> %s1, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
|
||||
store <8 x i32*> %interleaved.vec, <8 x i32*>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_undef_mask_factor2(<8 x i32>* %ptr) {
|
||||
; NEON-LABEL: @load_undef_mask_factor2(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <8 x i32>* %ptr to <4 x i32>*
|
||||
; NEON-NEXT: [[LDN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32(<4 x i32>* [[TMP1]])
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[LDN]], 1
|
||||
; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[LDN]], 0
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_undef_mask_factor2(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 4
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 6>
|
||||
%v1 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 7>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_undef_mask_factor3(<12 x i32>* %ptr) {
|
||||
; NEON-LABEL: @load_undef_mask_factor3(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <12 x i32>* %ptr to <4 x i32>*
|
||||
; NEON-NEXT: [[LDN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0v4i32(<4 x i32>* [[TMP1]])
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 2
|
||||
; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 1
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 0
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_undef_mask_factor3(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <12 x i32>, <12 x i32>* %ptr, align 4
|
||||
%v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
|
||||
%v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
|
||||
%v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_undef_mask_factor4(<16 x i32>* %ptr) {
|
||||
; NEON-LABEL: @load_undef_mask_factor4(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <16 x i32>* %ptr to <4 x i32>*
|
||||
; NEON-NEXT: [[LDN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4.v4i32.p0v4i32(<4 x i32>* [[TMP1]])
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 3
|
||||
; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 2
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 1
|
||||
; NEON-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[LDN]], 0
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_undef_mask_factor4(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <16 x i32>, <16 x i32>* %ptr, align 4
|
||||
%v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 undef, i32 undef>
|
||||
%v1 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 undef, i32 undef>
|
||||
%v2 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 undef, i32 undef>
|
||||
%v3 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 undef, i32 undef>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_undef_mask_factor2(<8 x i32>* %ptr, <4 x i32> %v0, <4 x i32> %v1) {
|
||||
; NEON-LABEL: @store_undef_mask_factor2(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> %v0, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> %v0, <4 x i32> %v1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = bitcast <8 x i32>* %ptr to <4 x i32>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32>* [[TMP3]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_undef_mask_factor2(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_undef_mask_factor3(<12 x i32>* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
|
||||
; NEON-LABEL: @store_undef_mask_factor3(
|
||||
; NEON: [[TMP1:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = bitcast <12 x i32>* %ptr to <4 x i32>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st3.v4i32.p0v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32>* [[TMP4]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_undef_mask_factor3(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%s1 = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
%interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <12 x i32> <i32 0, i32 4, i32 undef, i32 1, i32 undef, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_undef_mask_factor4(<16 x i32>* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
|
||||
; NEON-LABEL: @store_undef_mask_factor4(
|
||||
; NEON: [[TMP1:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = bitcast <16 x i32>* %ptr to <4 x i32>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st4.v4i32.p0v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32>* [[TMP5]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_undef_mask_factor4(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%s1 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 undef, i32 undef, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
|
||||
store <16 x i32> %interleaved.vec, <16 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_illegal_factor2(<3 x float>* %ptr) nounwind {
|
||||
; NEON-LABEL: @load_illegal_factor2(
|
||||
; NEON-NOT: @llvm.aarch64.neon
|
||||
; NEON: ret void
|
||||
; NO_NEON-LABEL: @load_illegal_factor2(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <3 x float>, <3 x float>* %ptr, align 16
|
||||
%v0 = shufflevector <3 x float> %interleaved.vec, <3 x float> undef, <3 x i32> <i32 0, i32 2, i32 undef>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_illegal_factor2(<3 x float>* %ptr, <3 x float> %v0) nounwind {
|
||||
; NEON-LABEL: @store_illegal_factor2(
|
||||
; NEON-NOT: @llvm.aarch64.neon
|
||||
; NEON: ret void
|
||||
; NO_NEON-LABEL: @store_illegal_factor2(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <3 x float> %v0, <3 x float> undef, <3 x i32> <i32 0, i32 2, i32 undef>
|
||||
store <3 x float> %interleaved.vec, <3 x float>* %ptr, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor4(<8 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor4(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 16, i32 17>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 32, i32 33>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 8, i32 9>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = bitcast <8 x i32>* %ptr to <2 x i32>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st4.v2i32.p0v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32>* [[TMP5]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor4(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 16, i32 32, i32 8, i32 5, i32 17, i32 33, i32 9>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor4_undefbeg(<8 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor4_undefbeg(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 16, i32 17>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 32, i32 33>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 8, i32 9>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = bitcast <8 x i32>* %ptr to <2 x i32>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st4.v2i32.p0v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32>* [[TMP5]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor4_undefbeg(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 undef, i32 16, i32 32, i32 8, i32 5, i32 17, i32 33, i32 9>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor4_undefend(<8 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor4_undefend(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 16, i32 17>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 32, i32 33>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 8, i32 9>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = bitcast <8 x i32>* %ptr to <2 x i32>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st4.v2i32.p0v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32>* [[TMP5]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor4_undefend(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 16, i32 32, i32 8, i32 5, i32 17, i32 33, i32 undef>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor4_undefmid(<8 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor4_undefmid(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 16, i32 17>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 32, i32 33>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 8, i32 9>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = bitcast <8 x i32>* %ptr to <2 x i32>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st4.v2i32.p0v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32>* [[TMP5]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor4_undefmid(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 undef, i32 32, i32 8, i32 5, i32 17, i32 undef, i32 9>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor4_undefmulti(<8 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor4_undefmulti(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 0, i32 1>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 0, i32 1>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 8, i32 9>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = bitcast <8 x i32>* %ptr to <2 x i32>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st4.v2i32.p0v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32>* [[TMP5]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor4_undefmulti(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 undef, i32 undef, i32 8, i32 undef, i32 undef, i32 undef, i32 9>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor3(<12 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor3(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 32, i32 33, i32 34, i32 35>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 16, i32 17, i32 18, i32 19>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = bitcast <12 x i32>* %ptr to <4 x i32>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st3.v4i32.p0v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32>* [[TMP4]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor3(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 4, i32 32, i32 16, i32 5, i32 33, i32 17, i32 6, i32 34, i32 18, i32 7, i32 35, i32 19>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor3_undefmultimid(<12 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor3_undefmultimid(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 32, i32 33, i32 34, i32 35>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 16, i32 17, i32 18, i32 19>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = bitcast <12 x i32>* %ptr to <4 x i32>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st3.v4i32.p0v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32>* [[TMP4]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor3_undefmultimid(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 4, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 7, i32 35, i32 19>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor3_undef_fail(<12 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor3_undef_fail(
|
||||
; NEON-NOT: @llvm.aarch64.neon
|
||||
; NEON: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor3_undef_fail(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 4, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 8, i32 35, i32 19>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor3_undeflane(<12 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor3_undeflane(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 32, i32 33, i32 34, i32 35>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 16, i32 17, i32 18, i32 19>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = bitcast <12 x i32>* %ptr to <4 x i32>*
|
||||
; NEON-NEXT: call void @llvm.aarch64.neon.st3.v4i32.p0v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32>* [[TMP4]])
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor3_undeflane(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 undef, i32 35, i32 19>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor3_negativestart(<12 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor3_negativestart(
|
||||
; NEON-NOT: @llvm.aarch64.neon
|
||||
; NEON: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor3_negativestart(
|
||||
; NO_NEON-NOT: @llvm.aarch64.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 2, i32 35, i32 19>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
if not 'AArch64' in config.root.targets:
|
||||
config.unsupported = True
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
; RUN: opt < %s -mattr=+neon -interleaved-access -S | FileCheck %s
|
||||
|
||||
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
|
||||
target triple = "arm---eabi"
|
||||
|
||||
define void @extract_user_basic(<8 x i32>* %ptr, i1 %c) {
|
||||
; CHECK-LABEL: @extract_user_basic(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i32>* %ptr to i8*
|
||||
; CHECK-NEXT: [[VLDN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8(i8* [[TMP0]], i32 8)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLDN]], 0
|
||||
; CHECK-NEXT: br i1 %c, label %if.then, label %if.merge
|
||||
; CHECK: if.then:
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
|
||||
; CHECK-NEXT: br label %if.merge
|
||||
; CHECK: if.merge:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 8
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
br i1 %c, label %if.then, label %if.merge
|
||||
|
||||
if.then:
|
||||
%e0 = extractelement <8 x i32> %interleaved.vec, i32 2
|
||||
br label %if.merge
|
||||
|
||||
if.merge:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @extract_user_multi(<8 x i32>* %ptr, i1 %c) {
|
||||
; CHECK-LABEL: @extract_user_multi(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i32>* %ptr to i8*
|
||||
; CHECK-NEXT: [[VLDN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8(i8* [[TMP0]], i32 8)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLDN]], 0
|
||||
; CHECK-NEXT: br i1 %c, label %if.then, label %if.merge
|
||||
; CHECK: if.then:
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
|
||||
; CHECK-NEXT: br label %if.merge
|
||||
; CHECK: if.merge:
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 8
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
br i1 %c, label %if.then, label %if.merge
|
||||
|
||||
if.then:
|
||||
%e0 = extractelement <8 x i32> %interleaved.vec, i32 0
|
||||
br label %if.merge
|
||||
|
||||
if.merge:
|
||||
%e1 = extractelement <8 x i32> %interleaved.vec, i32 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @extract_user_multi_no_dom(<8 x i32>* %ptr, i1 %c) {
|
||||
; CHECK-LABEL: @extract_user_multi_no_dom(
|
||||
; CHECK-NOT: @llvm.arm.neon
|
||||
; CHECK: ret void
|
||||
;
|
||||
entry:
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 8
|
||||
%e0 = extractelement <8 x i32> %interleaved.vec, i32 0
|
||||
br i1 %c, label %if.then, label %if.merge
|
||||
|
||||
if.then:
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%e1 = extractelement <8 x i32> %interleaved.vec, i32 2
|
||||
br label %if.merge
|
||||
|
||||
if.merge:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @extract_user_wrong_const_index(<8 x i32>* %ptr) {
|
||||
; CHECK-LABEL: @extract_user_wrong_const_index(
|
||||
; CHECK-NOT: @llvm.arm.neon
|
||||
; CHECK: ret void
|
||||
;
|
||||
entry:
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 8
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%e0 = extractelement <8 x i32> %interleaved.vec, i32 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @extract_user_undef_index(<8 x i32>* %ptr) {
|
||||
; CHECK-LABEL: @extract_user_undef_index(
|
||||
; CHECK-NOT: @llvm.arm.neon
|
||||
; CHECK: ret void
|
||||
;
|
||||
entry:
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 8
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%e0 = extractelement <8 x i32> %interleaved.vec, i32 undef
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @extract_user_var_index(<8 x i32>* %ptr, i32 %i) {
|
||||
; CHECK-LABEL: @extract_user_var_index(
|
||||
; CHECK-NOT: @llvm.arm.neon
|
||||
; CHECK: ret void
|
||||
;
|
||||
entry:
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 8
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%e0 = extractelement <8 x i32> %interleaved.vec, i32 %i
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,628 @@
|
|||
; RUN: opt < %s -mattr=+neon -interleaved-access -S | FileCheck %s -check-prefix=NEON
|
||||
; RUN: opt < %s -interleaved-access -S | FileCheck %s -check-prefix=NO_NEON
|
||||
|
||||
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
|
||||
target triple = "arm---eabi"
|
||||
|
||||
define void @load_factor2(<16 x i8>* %ptr) {
|
||||
; NEON-LABEL: @load_factor2(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <16 x i8>* %ptr to i8*
|
||||
; NEON-NEXT: [[VLDN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2.v8i8.p0i8(i8* [[TMP1]], i32 4)
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLDN]], 1
|
||||
; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLDN]], 0
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_factor2(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <16 x i8>, <16 x i8>* %ptr, align 4
|
||||
%v0 = shufflevector <16 x i8> %interleaved.vec, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
|
||||
%v1 = shufflevector <16 x i8> %interleaved.vec, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_factor3(<6 x i32>* %ptr) {
|
||||
; NEON-LABEL: @load_factor3(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <6 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[VLDN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3.v2i32.p0i8(i8* [[TMP1]], i32 4)
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 2
|
||||
; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 1
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 0
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_factor3(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <6 x i32>, <6 x i32>* %ptr, align 4
|
||||
%v0 = shufflevector <6 x i32> %interleaved.vec, <6 x i32> undef, <2 x i32> <i32 0, i32 3>
|
||||
%v1 = shufflevector <6 x i32> %interleaved.vec, <6 x i32> undef, <2 x i32> <i32 1, i32 4>
|
||||
%v2 = shufflevector <6 x i32> %interleaved.vec, <6 x i32> undef, <2 x i32> <i32 2, i32 5>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_factor4(<16 x i32>* %ptr) {
|
||||
; NEON-LABEL: @load_factor4(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <16 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[VLDN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4.v4i32.p0i8(i8* [[TMP1]], i32 4)
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLDN]], 3
|
||||
; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLDN]], 2
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLDN]], 1
|
||||
; NEON-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLDN]], 0
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_factor4(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <16 x i32>, <16 x i32>* %ptr, align 4
|
||||
%v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
|
||||
%v1 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
|
||||
%v2 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
|
||||
%v3 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_factor2(<16 x i8>* %ptr, <8 x i8> %v0, <8 x i8> %v1) {
|
||||
; NEON-LABEL: @store_factor2(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <16 x i8>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst2.p0i8.v8i8(i8* [[TMP1]], <8 x i8> [[TMP2]], <8 x i8> [[TMP3]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_factor2(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <8 x i8> %v0, <8 x i8> %v1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
|
||||
store <16 x i8> %interleaved.vec, <16 x i8>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_factor3(<12 x i32>* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
|
||||
; NEON-LABEL: @store_factor3(
|
||||
; NEON: [[TMP1:%.*]] = bitcast <12 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst3.p0i8.v4i32(i8* [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_factor3(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%s1 = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
%interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_factor4(<16 x i32>* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
|
||||
; NEON-LABEL: @store_factor4(
|
||||
; NEON: [[TMP1:%.*]] = bitcast <16 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst4.p0i8.v4i32(i8* [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_factor4(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%s1 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
|
||||
store <16 x i32> %interleaved.vec, <16 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_ptrvec_factor2(<4 x i32*>* %ptr) {
|
||||
; NEON-LABEL: @load_ptrvec_factor2(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <4 x i32*>* %ptr to i8*
|
||||
; NEON-NEXT: [[VLDN:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2.v2i32.p0i8(i8* [[TMP1]], i32 4)
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[VLDN]], 0
|
||||
; NEON-NEXT: [[TMP3:%.*]] = inttoptr <2 x i32> [[TMP2]] to <2 x i32*>
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_ptrvec_factor2(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <4 x i32*>, <4 x i32*>* %ptr, align 4
|
||||
%v0 = shufflevector <4 x i32*> %interleaved.vec, <4 x i32*> undef, <2 x i32> <i32 0, i32 2>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_ptrvec_factor3(<6 x i32*>* %ptr) {
|
||||
; NEON-LABEL: @load_ptrvec_factor3(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <6 x i32*>* %ptr to i8*
|
||||
; NEON-NEXT: [[VLDN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3.v2i32.p0i8(i8* [[TMP1]], i32 4)
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 2
|
||||
; NEON-NEXT: [[TMP3:%.*]] = inttoptr <2 x i32> [[TMP2]] to <2 x i32*>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 1
|
||||
; NEON-NEXT: [[TMP5:%.*]] = inttoptr <2 x i32> [[TMP4]] to <2 x i32*>
|
||||
; NEON-NEXT: [[TMP6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 0
|
||||
; NEON-NEXT: [[TMP7:%.*]] = inttoptr <2 x i32> [[TMP6]] to <2 x i32*>
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_ptrvec_factor3(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <6 x i32*>, <6 x i32*>* %ptr, align 4
|
||||
%v0 = shufflevector <6 x i32*> %interleaved.vec, <6 x i32*> undef, <2 x i32> <i32 0, i32 3>
|
||||
%v1 = shufflevector <6 x i32*> %interleaved.vec, <6 x i32*> undef, <2 x i32> <i32 1, i32 4>
|
||||
%v2 = shufflevector <6 x i32*> %interleaved.vec, <6 x i32*> undef, <2 x i32> <i32 2, i32 5>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_ptrvec_factor4(<8 x i32*>* %ptr) {
|
||||
; NEON-LABEL: @load_ptrvec_factor4(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <8 x i32*>* %ptr to i8*
|
||||
; NEON-NEXT: [[VLDN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld4.v2i32.p0i8(i8* [[TMP1]], i32 4)
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 3
|
||||
; NEON-NEXT: [[TMP3:%.*]] = inttoptr <2 x i32> [[TMP2]] to <2 x i32*>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 2
|
||||
; NEON-NEXT: [[TMP5:%.*]] = inttoptr <2 x i32> [[TMP4]] to <2 x i32*>
|
||||
; NEON-NEXT: [[TMP6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 1
|
||||
; NEON-NEXT: [[TMP7:%.*]] = inttoptr <2 x i32> [[TMP6]] to <2 x i32*>
|
||||
; NEON-NEXT: [[TMP8:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 0
|
||||
; NEON-NEXT: [[TMP9:%.*]] = inttoptr <2 x i32> [[TMP8]] to <2 x i32*>
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_ptrvec_factor4(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <8 x i32*>, <8 x i32*>* %ptr, align 4
|
||||
%v0 = shufflevector <8 x i32*> %interleaved.vec, <8 x i32*> undef, <2 x i32> <i32 0, i32 4>
|
||||
%v1 = shufflevector <8 x i32*> %interleaved.vec, <8 x i32*> undef, <2 x i32> <i32 1, i32 5>
|
||||
%v2 = shufflevector <8 x i32*> %interleaved.vec, <8 x i32*> undef, <2 x i32> <i32 2, i32 6>
|
||||
%v3 = shufflevector <8 x i32*> %interleaved.vec, <8 x i32*> undef, <2 x i32> <i32 3, i32 7>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_ptrvec_factor2(<4 x i32*>* %ptr, <2 x i32*> %v0, <2 x i32*> %v1) {
|
||||
; NEON-LABEL: @store_ptrvec_factor2(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = ptrtoint <2 x i32*> %v0 to <2 x i32>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = ptrtoint <2 x i32*> %v1 to <2 x i32>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = bitcast <4 x i32*>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> <i32 0, i32 1>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> <i32 2, i32 3>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst2.p0i8.v2i32(i8* [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_ptrvec_factor2(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
||||
store <4 x i32*> %interleaved.vec, <4 x i32*>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_ptrvec_factor3(<6 x i32*>* %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2) {
|
||||
; NEON-LABEL: @store_ptrvec_factor3(
|
||||
; NEON: [[TMP1:%.*]] = ptrtoint <4 x i32*> %s0 to <4 x i32>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = ptrtoint <4 x i32*> %s1 to <4 x i32>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = bitcast <6 x i32*>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <2 x i32> <i32 0, i32 1>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <2 x i32> <i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst3.p0i8.v2i32(i8* [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], <2 x i32> [[TMP6]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_ptrvec_factor3(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%s0 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%s1 = shufflevector <2 x i32*> %v2, <2 x i32*> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
|
||||
%interleaved.vec = shufflevector <4 x i32*> %s0, <4 x i32*> %s1, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
|
||||
store <6 x i32*> %interleaved.vec, <6 x i32*>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_ptrvec_factor4(<8 x i32*>* %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2, <2 x i32*> %v3) {
|
||||
; NEON-LABEL: @store_ptrvec_factor4(
|
||||
; NEON: [[TMP1:%.*]] = ptrtoint <4 x i32*> %s0 to <4 x i32>
|
||||
; NEON-NEXT: [[TMP2:%.*]] = ptrtoint <4 x i32*> %s1 to <4 x i32>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = bitcast <8 x i32*>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <2 x i32> <i32 0, i32 1>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <2 x i32> <i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <2 x i32> <i32 6, i32 7>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst4.p0i8.v2i32(i8* [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], <2 x i32> [[TMP6]], <2 x i32> [[TMP7]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_ptrvec_factor4(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%s0 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%s1 = shufflevector <2 x i32*> %v2, <2 x i32*> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%interleaved.vec = shufflevector <4 x i32*> %s0, <4 x i32*> %s1, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
|
||||
store <8 x i32*> %interleaved.vec, <8 x i32*>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_undef_mask_factor2(<8 x i32>* %ptr) {
|
||||
; NEON-LABEL: @load_undef_mask_factor2(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <8 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[VLDN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8(i8* [[TMP1]], i32 4)
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLDN]], 1
|
||||
; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLDN]], 0
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_undef_mask_factor2(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <8 x i32>, <8 x i32>* %ptr, align 4
|
||||
%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 6>
|
||||
%v1 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 7>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_undef_mask_factor3(<12 x i32>* %ptr) {
|
||||
; NEON-LABEL: @load_undef_mask_factor3(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <12 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[VLDN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3.v4i32.p0i8(i8* [[TMP1]], i32 4)
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLDN]], 2
|
||||
; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLDN]], 1
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLDN]], 0
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_undef_mask_factor3(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <12 x i32>, <12 x i32>* %ptr, align 4
|
||||
%v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
|
||||
%v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
|
||||
%v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_undef_mask_factor4(<16 x i32>* %ptr) {
|
||||
; NEON-LABEL: @load_undef_mask_factor4(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <16 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[VLDN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4.v4i32.p0i8(i8* [[TMP1]], i32 4)
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLDN]], 3
|
||||
; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLDN]], 2
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLDN]], 1
|
||||
; NEON-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLDN]], 0
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_undef_mask_factor4(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <16 x i32>, <16 x i32>* %ptr, align 4
|
||||
%v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 undef, i32 undef>
|
||||
%v1 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 undef, i32 undef>
|
||||
%v2 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 undef, i32 undef>
|
||||
%v3 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 undef, i32 undef>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_undef_mask_factor2(<8 x i32>* %ptr, <4 x i32> %v0, <4 x i32> %v1) {
|
||||
; NEON-LABEL: @store_undef_mask_factor2(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <8 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> %v0, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> %v0, <4 x i32> %v1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_undef_mask_factor2(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_undef_mask_factor3(<12 x i32>* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
|
||||
; NEON-LABEL: @store_undef_mask_factor3(
|
||||
; NEON: [[TMP1:%.*]] = bitcast <12 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst3.p0i8.v4i32(i8* [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_undef_mask_factor3(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%s1 = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
%interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <12 x i32> <i32 0, i32 4, i32 undef, i32 1, i32 undef, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_undef_mask_factor4(<16 x i32>* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
|
||||
; NEON-LABEL: @store_undef_mask_factor4(
|
||||
; NEON: [[TMP1:%.*]] = bitcast <16 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> %s0, <8 x i32> %s1, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst4.p0i8.v4i32(i8* [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_undef_mask_factor4(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%s1 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 undef, i32 undef, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
|
||||
store <16 x i32> %interleaved.vec, <16 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_address_space(<4 x i32> addrspace(1)* %ptr) {
|
||||
; NEON-LABEL: @load_address_space(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> addrspace(1)* %ptr to i8 addrspace(1)*
|
||||
; NEON-NEXT: [[VLDN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3.v2i32.p1i8(i8 addrspace(1)* [[TMP1]], i32 0)
|
||||
; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 2
|
||||
; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 1
|
||||
; NEON-NEXT: [[TMP4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 0
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @load_address_space(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <4 x i32>, <4 x i32> addrspace(1)* %ptr
|
||||
%v0 = shufflevector <4 x i32> %interleaved.vec, <4 x i32> undef, <2 x i32> <i32 0, i32 3>
|
||||
%v1 = shufflevector <4 x i32> %interleaved.vec, <4 x i32> undef, <2 x i32> <i32 1, i32 4>
|
||||
%v2 = shufflevector <4 x i32> %interleaved.vec, <4 x i32> undef, <2 x i32> <i32 2, i32 5>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_address_space(<4 x i32> addrspace(1)* %ptr, <2 x i32> %v0, <2 x i32> %v1) {
|
||||
; NEON-LABEL: @store_address_space(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> addrspace(1)* %ptr to i8 addrspace(1)*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> %v0, <2 x i32> %v1, <2 x i32> <i32 0, i32 1>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> %v0, <2 x i32> %v1, <2 x i32> <i32 2, i32 3>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst2.p1i8.v2i32(i8 addrspace(1)* [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], i32 0)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_address_space(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <2 x i32> %v0, <2 x i32> %v1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
||||
store <4 x i32> %interleaved.vec, <4 x i32> addrspace(1)* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load_illegal_factor2(<3 x float>* %ptr) nounwind {
|
||||
; NEON-LABEL: @load_illegal_factor2(
|
||||
; NEON-NOT: @llvm.arm.neon
|
||||
; NEON: ret void
|
||||
; NO_NEON-LABEL: @load_illegal_factor2(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = load <3 x float>, <3 x float>* %ptr, align 16
|
||||
%v0 = shufflevector <3 x float> %interleaved.vec, <3 x float> undef, <3 x i32> <i32 0, i32 2, i32 undef>
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_illegal_factor2(<3 x float>* %ptr, <3 x float> %v0) nounwind {
|
||||
; NEON-LABEL: @store_illegal_factor2(
|
||||
; NEON-NOT: @llvm.arm.neon
|
||||
; NEON: ret void
|
||||
; NO_NEON-LABEL: @store_illegal_factor2(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <3 x float> %v0, <3 x float> undef, <3 x i32> <i32 0, i32 2, i32 undef>
|
||||
store <3 x float> %interleaved.vec, <3 x float>* %ptr, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor4(<8 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor4(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <8 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 16, i32 17>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 32, i32 33>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 8, i32 9>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst4.p0i8.v2i32(i8* [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor4(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 16, i32 32, i32 8, i32 5, i32 17, i32 33, i32 9>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor4_undefbeg(<8 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor4_undefbeg(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <8 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 16, i32 17>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 32, i32 33>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 8, i32 9>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst4.p0i8.v2i32(i8* [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor4_undefbeg(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 undef, i32 16, i32 32, i32 8, i32 5, i32 17, i32 33, i32 9>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor4_undefend(<8 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor4_undefend(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <8 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 16, i32 17>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 32, i32 33>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 8, i32 9>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst4.p0i8.v2i32(i8* [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor4_undefend(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 16, i32 32, i32 8, i32 5, i32 17, i32 33, i32 undef>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor4_undefmid(<8 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor4_undefmid(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <8 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 16, i32 17>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 32, i32 33>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 8, i32 9>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst4.p0i8.v2i32(i8* [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor4_undefmid(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 undef, i32 32, i32 8, i32 5, i32 17, i32 undef, i32 9>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor4_undefmulti(<8 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor4_undefmulti(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <8 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 4, i32 5>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 0, i32 1>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 0, i32 1>
|
||||
; NEON-NEXT: [[TMP5:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <2 x i32> <i32 8, i32 9>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst4.p0i8.v2i32(i8* [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor4_undefmulti(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <8 x i32> <i32 4, i32 undef, i32 undef, i32 8, i32 undef, i32 undef, i32 undef, i32 9>
|
||||
store <8 x i32> %interleaved.vec, <8 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor3(<12 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor3(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <12 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 32, i32 33, i32 34, i32 35>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 16, i32 17, i32 18, i32 19>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst3.p0i8.v4i32(i8* [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor3(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 4, i32 32, i32 16, i32 5, i32 33, i32 17, i32 6, i32 34, i32 18, i32 7, i32 35, i32 19>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor3_undefmultimid(<12 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor3_undefmultimid(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <12 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 32, i32 33, i32 34, i32 35>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 16, i32 17, i32 18, i32 19>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst3.p0i8.v4i32(i8* [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor3_undefmultimid(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 4, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 7, i32 35, i32 19>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor3_undef_fail(<12 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor3_undef_fail(
|
||||
; NEON-NOT: @llvm.arm.neon
|
||||
; NEON: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor3_undef_fail(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 4, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 8, i32 35, i32 19>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor3_undeflane(<12 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor3_undeflane(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <12 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 32, i32 33, i32 34, i32 35>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 16, i32 17, i32 18, i32 19>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst3.p0i8.v4i32(i8* [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor3_undeflane(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 undef, i32 35, i32 19>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor3_endstart_fail(<12 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor3_endstart_fail(
|
||||
; NEON-NOT: @llvm.arm.neon
|
||||
; NEON: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor3_endstart_fail(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 2, i32 35, i32 19>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor3_endstart_pass(<12 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor3_endstart_pass(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <12 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 32, i32 33, i32 34, i32 35>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 16, i32 17, i32 18, i32 19>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst3.p0i8.v4i32(i8* [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor3_endstart_pass(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 undef, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 7, i32 35, i32 19>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor3_midstart_fail(<12 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor3_midstart_fail(
|
||||
; NEON-NOT: @llvm.arm.neon
|
||||
; NEON: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor3_midstart_fail(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 0, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 undef, i32 35, i32 19>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_general_mask_factor3_midstart_pass(<12 x i32>* %ptr, <32 x i32> %v0, <32 x i32> %v1) {
|
||||
; NEON-LABEL: @store_general_mask_factor3_midstart_pass(
|
||||
; NEON-NEXT: [[TMP1:%.*]] = bitcast <12 x i32>* %ptr to i8*
|
||||
; NEON-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; NEON-NEXT: [[TMP3:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 32, i32 33, i32 34, i32 35>
|
||||
; NEON-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> %v0, <32 x i32> %v1, <4 x i32> <i32 16, i32 17, i32 18, i32 19>
|
||||
; NEON-NEXT: call void @llvm.arm.neon.vst3.p0i8.v4i32(i8* [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], i32 4)
|
||||
; NEON-NEXT: ret void
|
||||
; NO_NEON-LABEL: @store_general_mask_factor3_midstart_pass(
|
||||
; NO_NEON-NOT: @llvm.arm.neon
|
||||
; NO_NEON: ret void
|
||||
;
|
||||
%interleaved.vec = shufflevector <32 x i32> %v0, <32 x i32> %v1, <12 x i32> <i32 undef, i32 32, i32 16, i32 1, i32 33, i32 17, i32 undef, i32 34, i32 18, i32 undef, i32 35, i32 19>
|
||||
store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
if not 'ARM' in config.root.targets:
|
||||
config.unsupported = True
|
||||
Loading…
Reference in New Issue