forked from OSchip/llvm-project
Create a new class, MemOperand, for describing memory references
in the backend. Introduce a new SDNode type, MemOperandSDNode, for holding a MemOperand in the SelectionDAG IR, and add a MemOperand list to MachineInstr, and code to manage them. Remove the offset field from SrcValueSDNode; uses of SrcValueSDNode that were using it are all all using MemOperandSDNode now. Also, begin updating some getLoad and getStore calls to use the PseudoSourceValue objects. Most of this was written by Florian Brander, some reorganization and updating to TOT by me. llvm-svn: 46585
This commit is contained in:
Dan Gohman
parent
b5474fc529
commit
3646fdda67
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@ -17,6 +17,7 @@
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#define LLVM_CODEGEN_MACHINEINSTR_H
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MemOperand.h"
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namespace llvm {
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@ -35,6 +36,7 @@ class MachineInstr {
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// are determined at construction time).
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std::vector<MachineOperand> Operands; // the operands
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std::vector<MemOperand> MemOperands; // information on memory references
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MachineInstr *Prev, *Next; // Links for MBB's intrusive list.
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MachineBasicBlock *Parent; // Pointer to the owning basic block.
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@ -94,6 +96,18 @@ public:
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///
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unsigned getNumExplicitOperands() const;
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/// Access to memory operands of the instruction
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unsigned getNumMemOperands() const { return MemOperands.size(); }
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const MemOperand& getMemOperand(unsigned i) const {
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assert(i < getNumMemOperands() && "getMemOperand() out of range!");
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return MemOperands[i];
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}
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MemOperand& getMemOperand(unsigned i) {
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assert(i < getNumMemOperands() && "getMemOperand() out of range!");
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return MemOperands[i];
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}
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/// isIdenticalTo - Return true if this instruction is identical to (same
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/// opcode and same operands as) the specified instruction.
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bool isIdenticalTo(const MachineInstr *Other) const {
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@ -192,6 +206,12 @@ public:
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///
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void RemoveOperand(unsigned i);
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/// addMemOperand - Add a MemOperand to the machine instruction, referencing
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/// arbitrary storage.
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void addMemOperand(const MemOperand &MO) {
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MemOperands.push_back(MO);
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}
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private:
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/// getRegInfo - If this instruction is embedded into a MachineFunction,
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/// return the MachineRegisterInfo object for the current function, otherwise
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@ -83,6 +83,12 @@ public:
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MI->addOperand(MachineOperand::CreateES(FnName, 0));
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return *this;
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}
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/// addMemOperand - Add a memory operand to the machine instruction.
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const MachineInstrBuilder &addMemOperand(const MemOperand &MO) const {
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MI->addMemOperand(MO);
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return *this;
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}
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};
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/// BuildMI - Builder interface. Specify how to create the initial instruction
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@ -0,0 +1,82 @@
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//===-- llvm/CodeGen/MemOperand.h - MemOperand class ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the declaration of the MemOperand class, which is a
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// description of a memory reference. It is used to help track dependencies
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// in the backend.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MEMOPERAND_H
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#define LLVM_CODEGEN_MEMOPERAND_H
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namespace llvm {
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class Value;
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//===----------------------------------------------------------------------===//
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/// MemOperand - A description of a memory reference used in the backend.
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/// Instead of holding a StoreInst or LoadInst, this class holds the address
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/// Value of the reference along with a byte size and offset. This allows it
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/// to describe lowered loads and stores. Also, the special PseudoSourceValue
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/// objects can be used to represent loads and stores to memory locations
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/// that aren't explicit in the regular LLVM IR.
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///
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class MemOperand {
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const Value *V;
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unsigned int Flags;
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int Offset;
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int Size;
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unsigned int Alignment;
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public:
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/// Flags values. These may be or'd together.
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enum MemOperandFlags {
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/// The memory access reads data.
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MOLoad = 1,
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/// The memory access writes data.
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MOStore = 2,
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/// The memory access is volatile.
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MOVolatile = 4
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};
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/// MemOperand - Construct an MemOperand object with the specified
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/// address Value, flags, offset, size, and alignment.
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MemOperand(const Value *v, unsigned int f, int o, int s, unsigned int a)
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: V(v), Flags(f), Offset(o), Size(s), Alignment(a) {}
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/// getValue - Return the base address of the memory access.
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/// Special values are PseudoSourceValue::FPRel, PseudoSourceValue::SPRel,
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/// and the other PseudoSourceValue members which indicate references to
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/// frame/stack pointer relative references and other special references.
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const Value *getValue() const { return V; }
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/// getFlags - Return the raw flags of the source value, \see MemOperandFlags.
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unsigned int getFlags() const { return Flags; }
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/// getOffset - For normal values, this is a byte offset added to the base
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/// address. For PseudoSourceValue::FPRel values, this is the FrameIndex
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/// number.
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int getOffset() const { return Offset; }
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/// getSize - Return the size in bytes of the memory reference.
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int getSize() const { return Size; }
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/// getAlignment - Return the minimum known alignment in bytes of the
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/// memory reference.
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unsigned int getAlignment() const { return Alignment; }
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bool isLoad() const { return Flags & MOLoad; }
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bool isStore() const { return Flags & MOStore; }
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bool isVolatile() const { return Flags & MOVolatile; }
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};
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} // End llvm namespace
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#endif
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@ -279,6 +279,7 @@ namespace llvm {
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if (isa<ConstantPoolSDNode>(Node)) return true;
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if (isa<JumpTableSDNode>(Node)) return true;
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if (isa<ExternalSymbolSDNode>(Node)) return true;
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if (isa<MemOperandSDNode>(Node)) return true;
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return false;
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}
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@ -312,11 +313,15 @@ namespace llvm {
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/// (which do not go into the machine instrs.)
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static unsigned CountResults(SDNode *Node);
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/// CountOperands The inputs to target nodes have any actual inputs first,
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/// followed by an optional chain operand, then flag operands. Compute the
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/// number of actual operands that will go into the machine instr.
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/// CountOperands - The inputs to target nodes have any actual inputs first,
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/// followed by optional memory operands chain operand, then flag operands.
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/// Compute the number of actual operands that will go into the machine
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/// instr.
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static unsigned CountOperands(SDNode *Node);
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/// CountMemOperands - Find the index of the last MemOperandSDNode
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static unsigned CountMemOperands(SDNode *Node);
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/// EmitNode - Generate machine code for an node and needed dependencies.
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/// VRBaseMap contains, for each already emitted node, the first virtual
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/// register number for the results of the node.
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@ -357,6 +362,8 @@ namespace llvm {
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void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDOperand, unsigned> &VRBaseMap);
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void AddMemOperand(MachineInstr *MI, const MemOperand &MO);
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};
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/// createBURRListDAGScheduler - This creates a bottom up register usage
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@ -381,8 +381,12 @@ public:
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SDOperand getIndexedStore(SDOperand OrigStoe, SDOperand Base,
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SDOperand Offset, ISD::MemIndexedMode AM);
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// getSrcValue - construct a node to track a Value* through the backend
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SDOperand getSrcValue(const Value* I, int offset = 0);
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// getSrcValue - Construct a node to track a Value* through the backend.
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SDOperand getSrcValue(const Value *v);
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// getMemOperand - Construct a node to track a memory reference
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// through the backend.
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SDOperand getMemOperand(const MemOperand &MO);
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/// UpdateNodeOperands - *Mutate* the specified node in-place to have the
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/// specified operands. If the resultant node already exists in the DAG,
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@ -25,6 +25,7 @@
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#include "llvm/ADT/iterator"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MemOperand.h"
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#include "llvm/Support/DataTypes.h"
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#include <cassert>
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@ -534,11 +535,15 @@ namespace ISD {
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// pointer, and a SRCVALUE.
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VAEND, VASTART,
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// SRCVALUE - This corresponds to a Value*, and is used to associate memory
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// locations with their value. This allows one use alias analysis
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// information in the backend.
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// SRCVALUE - This is a node type that holds a Value* that is used to
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// make reference to a value in the LLVM IR.
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SRCVALUE,
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// MEMOPERAND - This is a node that contains a MemOperand which records
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// information about a memory reference. This is used to make AliasAnalysis
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// queries from the backend.
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MEMOPERAND,
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// PCMARKER - This corresponds to the pcmarker intrinsic.
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PCMARKER,
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@ -1378,17 +1383,16 @@ public:
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class SrcValueSDNode : public SDNode {
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const Value *V;
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int offset;
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virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
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protected:
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friend class SelectionDAG;
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SrcValueSDNode(const Value* v, int o)
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: SDNode(ISD::SRCVALUE, getSDVTList(MVT::Other)), V(v), offset(o) {
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}
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/// Create a SrcValue for a general value.
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explicit SrcValueSDNode(const Value *v)
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: SDNode(ISD::SRCVALUE, getSDVTList(MVT::Other)), V(v) {}
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public:
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/// getValue - return the contained Value.
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const Value *getValue() const { return V; }
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int getOffset() const { return offset; }
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static bool classof(const SrcValueSDNode *) { return true; }
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static bool classof(const SDNode *N) {
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@ -1397,6 +1401,29 @@ public:
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};
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/// MemOperandSDNode - An SDNode that holds a MemOperand. This is
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/// used to represent a reference to memory after ISD::LOAD
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/// and ISD::STORE have been lowered.
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///
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class MemOperandSDNode : public SDNode {
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virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
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protected:
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friend class SelectionDAG;
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/// Create a MemOperand node
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explicit MemOperandSDNode(MemOperand mo)
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: SDNode(ISD::MEMOPERAND, getSDVTList(MVT::Other)), MO(mo) {}
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public:
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/// MO - The contained MemOperand.
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const MemOperand MO;
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static bool classof(const MemOperandSDNode *) { return true; }
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static bool classof(const SDNode *N) {
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return N->getOpcode() == ISD::MEMOPERAND;
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}
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};
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class RegisterSDNode : public SDNode {
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unsigned Reg;
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virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
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@ -1546,6 +1573,10 @@ public:
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/// isUnindexed - Return true if this is NOT a pre/post inc/dec load/store.
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bool isUnindexed() const { return AddrMode == ISD::UNINDEXED; }
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/// getMemOperand - Return a MemOperand object describing the memory
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/// reference performed by this load or store.
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MemOperand getMemOperand() const;
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static bool classof(const LSBaseSDNode *N) { return true; }
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static bool classof(const SDNode *N) {
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return N->getOpcode() == ISD::LOAD ||
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@ -15,6 +15,8 @@
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#include "llvm/Value.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrDesc.h"
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#include "llvm/Target/MRegisterInfo.h"
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@ -291,6 +293,7 @@ MachineInstr::MachineInstr(const MachineInstr &MI) {
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TID = &MI.getDesc();
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NumImplicitOps = MI.NumImplicitOps;
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Operands.reserve(MI.getNumOperands());
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MemOperands = MI.MemOperands;
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// Add operands
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for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
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@ -620,6 +623,34 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
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getOperand(i).print(OS, TM);
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}
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if (getNumMemOperands() > 0) {
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OS << ", SV:";
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for (unsigned i = 0; i < getNumMemOperands(); i++) {
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const MemOperand &MRO = getMemOperand(i);
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const Value *V = MRO.getValue();
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assert(V && "SV missing.");
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assert((MRO.isLoad() || MRO.isStore()) &&
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"SV has to be a load, store or both.");
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if (MRO.isVolatile())
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OS << "Volatile";
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if (MRO.isLoad())
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OS << "LD";
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if (MRO.isStore())
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OS << "ST";
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OS << MRO.getSize();
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if (!V->getName().empty())
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OS << "[" << V->getName() << " + " << MRO.getOffset() << "]";
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else if (isa<PseudoSourceValue>(V))
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OS << "[" << *V << " + " << MRO.getOffset() << "]";
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else
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OS << "[" << V << " + " << MRO.getOffset() << "]";
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}
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}
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OS << "\n";
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}
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@ -16,6 +16,7 @@
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetData.h"
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@ -509,9 +510,10 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
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SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
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if (Extend) {
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return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
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CPIdx, NULL, 0, MVT::f32);
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CPIdx, &PseudoSourceValue::CPRel, 0, MVT::f32);
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} else {
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return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
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return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
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&PseudoSourceValue::CPRel, 0);
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}
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}
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@ -796,6 +798,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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case ISD::TargetExternalSymbol:
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case ISD::VALUETYPE:
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case ISD::SRCVALUE:
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case ISD::MEMOPERAND:
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case ISD::STRING:
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case ISD::CONDCODE:
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// Primitives must all be legal.
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@ -1301,8 +1304,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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MVT::ValueType IdxVT = Tmp3.getValueType();
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MVT::ValueType PtrVT = TLI.getPointerTy();
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SDOperand StackPtr = DAG.CreateStackTemporary(VT);
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FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(StackPtr.Val);
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assert(StackPtrFI);
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int SPFI = StackPtrFI->getIndex();
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// Store the vector.
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SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
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SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
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&PseudoSourceValue::FPRel, SPFI);
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// Truncate or zero extend offset to target pointer type.
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unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
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@ -1312,9 +1321,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
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SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
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// Store the scalar value.
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Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
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Ch = DAG.getStore(Ch, Tmp2, StackPtr2, &PseudoSourceValue::FPRel, SPFI);
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// Load the updated vector.
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Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
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Result = DAG.getLoad(VT, Ch, StackPtr, &PseudoSourceValue::FPRel, SPFI);
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break;
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}
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}
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@ -1663,8 +1672,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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SDOperand LD;
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switch (EntrySize) {
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default: assert(0 && "Size of jump table not supported yet."); break;
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case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
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case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
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case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
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&PseudoSourceValue::JTRel, 0); break;
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case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
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&PseudoSourceValue::JTRel, 0); break;
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}
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Addr = LD;
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@ -3225,16 +3236,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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}
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break;
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case TargetLowering::Expand: {
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SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
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SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
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SV->getValue(), SV->getOffset());
|
||||
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
|
||||
SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
|
||||
// Increment the pointer, VAList, to the next vaarg
|
||||
Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
|
||||
DAG.getConstant(MVT::getSizeInBits(VT)/8,
|
||||
TLI.getPointerTy()));
|
||||
// Store the incremented VAList to the legalized pointer
|
||||
Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
|
||||
SV->getOffset());
|
||||
Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
|
||||
// Load the actual argument out of the pointer VAList
|
||||
Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
|
||||
Tmp1 = LegalizeOp(Result.getValue(1));
|
||||
|
|
@ -3270,12 +3279,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
|
|||
case TargetLowering::Expand:
|
||||
// This defaults to loading a pointer from the input and storing it to the
|
||||
// output, returning the chain.
|
||||
SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
|
||||
SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
|
||||
Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
|
||||
SVD->getOffset());
|
||||
Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
|
||||
SVS->getOffset());
|
||||
const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
|
||||
const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
|
||||
Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0);
|
||||
Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
|
@ -4270,16 +4277,14 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
|
|||
Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
|
||||
Result = TLI.CustomPromoteOperation(Tmp3, DAG);
|
||||
} else {
|
||||
SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
|
||||
SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
|
||||
SV->getValue(), SV->getOffset());
|
||||
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
|
||||
SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
|
||||
// Increment the pointer, VAList, to the next vaarg
|
||||
Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
|
||||
DAG.getConstant(MVT::getSizeInBits(VT)/8,
|
||||
TLI.getPointerTy()));
|
||||
// Store the incremented VAList to the legalized pointer
|
||||
Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
|
||||
SV->getOffset());
|
||||
Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
|
||||
// Load the actual argument out of the pointer VAList
|
||||
Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
|
||||
}
|
||||
|
|
@ -4735,6 +4740,10 @@ SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
|
|||
// Create the stack frame object.
|
||||
SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
|
||||
|
||||
FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(FIPtr);
|
||||
assert(StackPtrFI);
|
||||
int SPFI = StackPtrFI->getIndex();
|
||||
|
||||
unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
|
||||
unsigned SlotSize = MVT::getSizeInBits(SlotVT);
|
||||
unsigned DestSize = MVT::getSizeInBits(DestVT);
|
||||
|
|
@ -4743,10 +4752,12 @@ SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
|
|||
// later than DestVT.
|
||||
SDOperand Store;
|
||||
if (SrcSize > SlotSize)
|
||||
Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0,SlotVT);
|
||||
Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
|
||||
&PseudoSourceValue::FPRel, SPFI, SlotVT);
|
||||
else {
|
||||
assert(SrcSize == SlotSize && "Invalid store");
|
||||
Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
|
||||
Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
|
||||
&PseudoSourceValue::FPRel, SPFI, SlotVT);
|
||||
}
|
||||
|
||||
// Result is a load from the stack slot.
|
||||
|
|
@ -4761,9 +4772,15 @@ SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
|
|||
// Create a vector sized/aligned stack slot, store the value to element #0,
|
||||
// then load the whole vector back out.
|
||||
SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
|
||||
|
||||
FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(StackPtr);
|
||||
assert(StackPtrFI);
|
||||
int SPFI = StackPtrFI->getIndex();
|
||||
|
||||
SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
|
||||
NULL, 0);
|
||||
return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
|
||||
&PseudoSourceValue::FPRel, SPFI);
|
||||
return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
|
||||
&PseudoSourceValue::FPRel, SPFI);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -4827,7 +4844,8 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
|
|||
}
|
||||
Constant *CP = ConstantVector::get(CV);
|
||||
SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
|
||||
return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
|
||||
return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
|
||||
&PseudoSourceValue::CPRel, 0);
|
||||
}
|
||||
|
||||
if (SplatValue.Val) { // Splat of one value?
|
||||
|
|
@ -5169,11 +5187,13 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
|
|||
CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
|
||||
SDOperand FudgeInReg;
|
||||
if (DestTy == MVT::f32)
|
||||
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
|
||||
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
|
||||
&PseudoSourceValue::CPRel, 0);
|
||||
else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
|
||||
// FIXME: Avoid the extend by construction the right constantpool?
|
||||
FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
|
||||
CPIdx, NULL, 0, MVT::f32);
|
||||
CPIdx, &PseudoSourceValue::CPRel, 0,
|
||||
MVT::f32);
|
||||
else
|
||||
assert(0 && "Unexpected conversion");
|
||||
|
||||
|
|
@ -5315,11 +5335,13 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
|
|||
CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
|
||||
SDOperand FudgeInReg;
|
||||
if (DestVT == MVT::f32)
|
||||
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
|
||||
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
|
||||
&PseudoSourceValue::CPRel, 0);
|
||||
else {
|
||||
FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
|
||||
DAG.getEntryNode(), CPIdx,
|
||||
NULL, 0, MVT::f32));
|
||||
&PseudoSourceValue::CPRel, 0,
|
||||
MVT::f32));
|
||||
}
|
||||
|
||||
return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
|
||||
|
|
@ -6728,10 +6750,14 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
|
|||
// Lower to a store/load so that it can be split.
|
||||
// FIXME: this could be improved probably.
|
||||
SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
|
||||
FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr.Val);
|
||||
assert(FI && "Expecting CreateStackTemporary to return a frame index.\n");
|
||||
|
||||
SDOperand St = DAG.getStore(DAG.getEntryNode(),
|
||||
InOp, Ptr, NULL, 0);
|
||||
InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
|
||||
InOp, Ptr,
|
||||
&PseudoSourceValue::FPRel, FI->getIndex());
|
||||
InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
|
||||
&PseudoSourceValue::FPRel, FI->getIndex());
|
||||
}
|
||||
// Split the vector and convert each of the pieces now.
|
||||
SplitVectorOp(InOp, Lo, Hi);
|
||||
|
|
|
|||
|
|
@ -277,10 +277,22 @@ unsigned ScheduleDAG::CountResults(SDNode *Node) {
|
|||
return N;
|
||||
}
|
||||
|
||||
/// CountOperands The inputs to target nodes have any actual inputs first,
|
||||
/// followed by an optional chain operand, then flag operands. Compute the
|
||||
/// number of actual operands that will go into the machine instr.
|
||||
/// CountOperands - The inputs to target nodes have any actual inputs first,
|
||||
/// followed by optional memory operands chain operand, then flag operands.
|
||||
/// Compute the number of actual operands that will go into the machine istr.
|
||||
unsigned ScheduleDAG::CountOperands(SDNode *Node) {
|
||||
unsigned N = Node->getNumOperands();
|
||||
while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
|
||||
--N;
|
||||
if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
|
||||
--N; // Ignore chain if it exists.
|
||||
while (N && MemOperandSDNode::classof(Node->getOperand(N - 1).Val))
|
||||
--N; // Ignore MemOperand nodes
|
||||
return N;
|
||||
}
|
||||
|
||||
/// CountMemOperands - Find the index of the last MemOperandSDNode operand
|
||||
unsigned ScheduleDAG::CountMemOperands(SDNode *Node) {
|
||||
unsigned N = Node->getNumOperands();
|
||||
while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
|
||||
--N;
|
||||
|
|
@ -517,6 +529,10 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
|
|||
|
||||
}
|
||||
|
||||
void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MemOperand &MO) {
|
||||
MI->addMemOperand(MO);
|
||||
}
|
||||
|
||||
// Returns the Register Class of a subregister
|
||||
static const TargetRegisterClass *getSubRegisterRegClass(
|
||||
const TargetRegisterClass *TRC,
|
||||
|
|
@ -674,6 +690,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
|
|||
|
||||
unsigned NumResults = CountResults(Node);
|
||||
unsigned NodeOperands = CountOperands(Node);
|
||||
unsigned NodeMemOperands = CountMemOperands(Node);
|
||||
unsigned NumMIOperands = NodeOperands + NumResults;
|
||||
bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
|
||||
II.getImplicitDefs() != 0;
|
||||
|
|
@ -696,6 +713,10 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
|
|||
for (unsigned i = 0; i != NodeOperands; ++i)
|
||||
AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
|
||||
|
||||
// Emit all of the memory operands of this instruction
|
||||
for (unsigned i = NodeOperands; i != NodeMemOperands; ++i)
|
||||
AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO);
|
||||
|
||||
// Commute node if it has been determined to be profitable.
|
||||
if (CommuteSet.count(Node)) {
|
||||
MachineInstr *NewMI = TII->commuteInstruction(MI);
|
||||
|
|
@ -754,6 +775,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
|
|||
case ISD::EntryToken: // fall thru
|
||||
case ISD::TokenFactor:
|
||||
case ISD::LABEL:
|
||||
case ISD::SRCVALUE:
|
||||
break;
|
||||
case ISD::CopyToReg: {
|
||||
unsigned InReg;
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineConstantPool.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/PseudoSourceValue.h"
|
||||
#include "llvm/Support/MathExtras.h"
|
||||
#include "llvm/Target/MRegisterInfo.h"
|
||||
#include "llvm/Target/TargetData.h"
|
||||
|
|
@ -342,10 +343,16 @@ static void AddNodeIDNode(FoldingSetNodeID &ID, SDNode *N) {
|
|||
case ISD::Register:
|
||||
ID.AddInteger(cast<RegisterSDNode>(N)->getReg());
|
||||
break;
|
||||
case ISD::SRCVALUE: {
|
||||
SrcValueSDNode *SV = cast<SrcValueSDNode>(N);
|
||||
ID.AddPointer(SV->getValue());
|
||||
ID.AddInteger(SV->getOffset());
|
||||
case ISD::SRCVALUE:
|
||||
ID.AddPointer(cast<SrcValueSDNode>(N)->getValue());
|
||||
break;
|
||||
case ISD::MEMOPERAND: {
|
||||
const MemOperand &MO = cast<MemOperandSDNode>(N)->MO;
|
||||
ID.AddPointer(MO.getValue());
|
||||
ID.AddInteger(MO.getFlags());
|
||||
ID.AddInteger(MO.getOffset());
|
||||
ID.AddInteger(MO.getSize());
|
||||
ID.AddInteger(MO.getAlignment());
|
||||
break;
|
||||
}
|
||||
case ISD::FrameIndex:
|
||||
|
|
@ -916,18 +923,42 @@ SDOperand SelectionDAG::getRegister(unsigned RegNo, MVT::ValueType VT) {
|
|||
return SDOperand(N, 0);
|
||||
}
|
||||
|
||||
SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) {
|
||||
SDOperand SelectionDAG::getSrcValue(const Value *V) {
|
||||
assert((!V || isa<PointerType>(V->getType())) &&
|
||||
"SrcValue is not a pointer?");
|
||||
|
||||
FoldingSetNodeID ID;
|
||||
AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0);
|
||||
ID.AddPointer(V);
|
||||
ID.AddInteger(Offset);
|
||||
|
||||
void *IP = 0;
|
||||
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
|
||||
return SDOperand(E, 0);
|
||||
SDNode *N = new SrcValueSDNode(V, Offset);
|
||||
|
||||
SDNode *N = new SrcValueSDNode(V);
|
||||
CSEMap.InsertNode(N, IP);
|
||||
AllNodes.push_back(N);
|
||||
return SDOperand(N, 0);
|
||||
}
|
||||
|
||||
SDOperand SelectionDAG::getMemOperand(const MemOperand &MO) {
|
||||
const Value *v = MO.getValue();
|
||||
assert((!v || isa<PointerType>(v->getType())) &&
|
||||
"SrcValue is not a pointer?");
|
||||
|
||||
FoldingSetNodeID ID;
|
||||
AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0);
|
||||
ID.AddPointer(v);
|
||||
ID.AddInteger(MO.getFlags());
|
||||
ID.AddInteger(MO.getOffset());
|
||||
ID.AddInteger(MO.getSize());
|
||||
ID.AddInteger(MO.getAlignment());
|
||||
|
||||
void *IP = 0;
|
||||
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
|
||||
return SDOperand(E, 0);
|
||||
|
||||
SDNode *N = new MemOperandSDNode(MO);
|
||||
CSEMap.InsertNode(N, IP);
|
||||
AllNodes.push_back(N);
|
||||
return SDOperand(N, 0);
|
||||
|
|
@ -3417,6 +3448,7 @@ void JumpTableSDNode::ANCHOR() {}
|
|||
void ConstantPoolSDNode::ANCHOR() {}
|
||||
void BasicBlockSDNode::ANCHOR() {}
|
||||
void SrcValueSDNode::ANCHOR() {}
|
||||
void MemOperandSDNode::ANCHOR() {}
|
||||
void RegisterSDNode::ANCHOR() {}
|
||||
void ExternalSymbolSDNode::ANCHOR() {}
|
||||
void CondCodeSDNode::ANCHOR() {}
|
||||
|
|
@ -3441,6 +3473,26 @@ GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA,
|
|||
TheGlobal = const_cast<GlobalValue*>(GA);
|
||||
}
|
||||
|
||||
/// getMemOperand - Return a MemOperand object describing the memory
|
||||
/// reference performed by this load or store.
|
||||
MemOperand LSBaseSDNode::getMemOperand() const {
|
||||
int Size = (MVT::getSizeInBits(getMemoryVT()) + 7) >> 3;
|
||||
int Flags =
|
||||
getOpcode() == ISD::LOAD ? MemOperand::MOLoad : MemOperand::MOStore;
|
||||
if (IsVolatile) Flags |= MemOperand::MOVolatile;
|
||||
|
||||
// Check if the load references a frame index, and does not have
|
||||
// an SV attached.
|
||||
const FrameIndexSDNode *FI =
|
||||
dyn_cast<const FrameIndexSDNode>(getBasePtr().Val);
|
||||
if (!getSrcValue() && FI)
|
||||
return MemOperand(&PseudoSourceValue::FPRel, Flags,
|
||||
FI->getIndex(), Size, Alignment);
|
||||
else
|
||||
return MemOperand(getSrcValue(), Flags,
|
||||
getSrcValueOffset(), Size, Alignment);
|
||||
}
|
||||
|
||||
/// Profile - Gather unique data for the node.
|
||||
///
|
||||
void SDNode::Profile(FoldingSetNodeID &ID) {
|
||||
|
|
@ -3633,6 +3685,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
|
|||
case ISD::PCMARKER: return "PCMarker";
|
||||
case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
|
||||
case ISD::SRCVALUE: return "SrcValue";
|
||||
case ISD::MEMOPERAND: return "MemOperand";
|
||||
case ISD::EntryToken: return "EntryToken";
|
||||
case ISD::TokenFactor: return "TokenFactor";
|
||||
case ISD::AssertSext: return "AssertSext";
|
||||
|
|
@ -3937,9 +3990,14 @@ void SDNode::dump(const SelectionDAG *G) const {
|
|||
cerr << "'" << ES->getSymbol() << "'";
|
||||
} else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) {
|
||||
if (M->getValue())
|
||||
cerr << "<" << M->getValue() << ":" << M->getOffset() << ">";
|
||||
cerr << "<" << M->getValue() << ">";
|
||||
else
|
||||
cerr << "<null:" << M->getOffset() << ">";
|
||||
cerr << "<null>";
|
||||
} else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) {
|
||||
if (M->MO.getValue())
|
||||
cerr << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">";
|
||||
else
|
||||
cerr << "<null:" << M->MO.getOffset() << ">";
|
||||
} else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) {
|
||||
cerr << ":" << MVT::getValueTypeString(N->getVT());
|
||||
} else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) {
|
||||
|
|
|
|||
|
|
@ -142,9 +142,14 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
|
|||
Op += "'" + std::string(ES->getSymbol()) + "'";
|
||||
} else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(Node)) {
|
||||
if (M->getValue())
|
||||
Op += "<" + M->getValue()->getName() + ":" + itostr(M->getOffset()) + ">";
|
||||
Op += "<" + M->getValue()->getName() + ">";
|
||||
else
|
||||
Op += "<null:" + itostr(M->getOffset()) + ">";
|
||||
Op += "<null>";
|
||||
} else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(Node)) {
|
||||
if (M->MO.getValue())
|
||||
Op += "<" + M->MO.getValue()->getName() + ":" + itostr(M->MO.getOffset()) + ">";
|
||||
else
|
||||
Op += "<null:" + itostr(M->MO.getOffset()) + ">";
|
||||
} else if (const VTSDNode *N = dyn_cast<VTSDNode>(Node)) {
|
||||
Op = Op + " VT=" + MVT::getValueTypeString(N->getVT());
|
||||
} else if (const StringSDNode *N = dyn_cast<StringSDNode>(Node)) {
|
||||
|
|
|
|||
|
|
@ -911,9 +911,8 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
|
|||
// memory location argument.
|
||||
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
||||
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
|
||||
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
|
||||
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
|
||||
SV->getOffset());
|
||||
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
||||
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
|
||||
}
|
||||
|
||||
static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
|
||||
|
|
|
|||
|
|
@ -491,10 +491,9 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
|||
case ISD::VAARG: {
|
||||
SDOperand Chain = Op.getOperand(0);
|
||||
SDOperand VAListP = Op.getOperand(1);
|
||||
SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
|
||||
const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
||||
|
||||
SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS->getValue(),
|
||||
VAListS->getOffset());
|
||||
SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0);
|
||||
SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
|
||||
DAG.getConstant(8, MVT::i64));
|
||||
SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
|
||||
|
|
@ -527,13 +526,11 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
|||
SDOperand Chain = Op.getOperand(0);
|
||||
SDOperand DestP = Op.getOperand(1);
|
||||
SDOperand SrcP = Op.getOperand(2);
|
||||
SrcValueSDNode *DestS = cast<SrcValueSDNode>(Op.getOperand(3));
|
||||
SrcValueSDNode *SrcS = cast<SrcValueSDNode>(Op.getOperand(4));
|
||||
const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
|
||||
const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
|
||||
|
||||
SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
|
||||
SrcS->getValue(), SrcS->getOffset());
|
||||
SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS->getValue(),
|
||||
DestS->getOffset());
|
||||
SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0);
|
||||
SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0);
|
||||
SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
|
||||
DAG.getConstant(8, MVT::i64));
|
||||
Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
|
||||
|
|
@ -544,12 +541,11 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
|||
case ISD::VASTART: {
|
||||
SDOperand Chain = Op.getOperand(0);
|
||||
SDOperand VAListP = Op.getOperand(1);
|
||||
SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
|
||||
const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
||||
|
||||
// vastart stores the address of the VarArgsBase and VarArgsOffset
|
||||
SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
|
||||
SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS->getValue(),
|
||||
VAListS->getOffset());
|
||||
SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0);
|
||||
SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
|
||||
DAG.getConstant(8, MVT::i64));
|
||||
return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
|
||||
|
|
|
|||
|
|
@ -581,16 +581,16 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
|||
}
|
||||
case ISD::VAARG: {
|
||||
MVT::ValueType VT = getPointerTy();
|
||||
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
|
||||
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
||||
SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
|
||||
SV->getValue(), SV->getOffset());
|
||||
SV, 0);
|
||||
// Increment the pointer, VAList, to the next vaarg
|
||||
SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
|
||||
DAG.getConstant(MVT::getSizeInBits(VT)/8,
|
||||
VT));
|
||||
// Store the incremented VAList to the legalized pointer
|
||||
VAIncr = DAG.getStore(VAList.getValue(1), VAIncr,
|
||||
Op.getOperand(1), SV->getValue(), SV->getOffset());
|
||||
Op.getOperand(1), SV, 0);
|
||||
// Load the actual argument out of the pointer VAList
|
||||
return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0);
|
||||
}
|
||||
|
|
@ -598,9 +598,8 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
|||
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
||||
// memory location argument.
|
||||
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
|
||||
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
|
||||
return DAG.getStore(Op.getOperand(0), FR,
|
||||
Op.getOperand(1), SV->getValue(), SV->getOffset());
|
||||
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
||||
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
|
||||
}
|
||||
// Frame & Return address. Currently unimplemented
|
||||
case ISD::RETURNADDR: break;
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/PseudoSourceValue.h"
|
||||
#include "llvm/CodeGen/SelectionDAG.h"
|
||||
#include "llvm/Constants.h"
|
||||
#include "llvm/Function.h"
|
||||
|
|
@ -1172,9 +1173,8 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
|
|||
// memory location argument.
|
||||
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
||||
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
|
||||
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
|
||||
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
|
||||
SV->getOffset());
|
||||
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
||||
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
|
||||
}
|
||||
|
||||
// For ELF 32 ABI we follow the layout of the va_list struct.
|
||||
|
|
@ -1208,37 +1208,41 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
|
|||
|
||||
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
||||
|
||||
SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
|
||||
SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
|
||||
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
|
||||
|
||||
SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8,
|
||||
PtrVT);
|
||||
SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1,
|
||||
PtrVT);
|
||||
SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT);
|
||||
uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8;
|
||||
SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
|
||||
|
||||
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
|
||||
uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1;
|
||||
SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
|
||||
|
||||
uint64_t FPROffset = 1;
|
||||
SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
|
||||
|
||||
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
||||
|
||||
// Store first byte : number of int regs
|
||||
SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
|
||||
Op.getOperand(1), SV->getValue(),
|
||||
SV->getOffset());
|
||||
Op.getOperand(1), SV, 0);
|
||||
uint64_t nextOffset = FPROffset;
|
||||
SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
|
||||
ConstFPROffset);
|
||||
|
||||
// Store second byte : number of float regs
|
||||
SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr,
|
||||
SV->getValue(), SV->getOffset());
|
||||
SDOperand secondStore =
|
||||
DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
|
||||
nextOffset += StackOffset;
|
||||
nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
|
||||
|
||||
// Store second word : arguments given on stack
|
||||
SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr,
|
||||
SV->getValue(), SV->getOffset());
|
||||
SDOperand thirdStore =
|
||||
DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
|
||||
nextOffset += FrameOffset;
|
||||
nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
|
||||
|
||||
// Store third word : arguments given in registers
|
||||
return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(),
|
||||
SV->getOffset());
|
||||
return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -2196,9 +2200,11 @@ static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
|
|||
Op.getOperand(0));
|
||||
|
||||
// STD the extended value into the stack slot.
|
||||
MemOperand MO(&PseudoSourceValue::FPRel,
|
||||
MemOperand::MOStore, FrameIdx, 8, 8);
|
||||
SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
|
||||
DAG.getEntryNode(), Ext64, FIdx,
|
||||
DAG.getSrcValue(NULL));
|
||||
DAG.getMemOperand(MO));
|
||||
// Load the value as a double.
|
||||
SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
|
||||
|
||||
|
|
@ -3297,11 +3303,11 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
|
|||
std::vector<MVT::ValueType> VTs;
|
||||
VTs.push_back(MVT::i32);
|
||||
VTs.push_back(MVT::Other);
|
||||
SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset());
|
||||
SDOperand MO = DAG.getMemOperand(LD->getMemOperand());
|
||||
SDOperand Ops[] = {
|
||||
LD->getChain(), // Chain
|
||||
LD->getBasePtr(), // Ptr
|
||||
SV, // SrcValue
|
||||
MO, // MemOperand
|
||||
DAG.getValueType(N->getValueType(0)) // VT
|
||||
};
|
||||
SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
|
||||
|
|
|
|||
|
|
@ -804,25 +804,23 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
|||
SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
|
||||
DAG.getRegister(SP::I6, MVT::i32),
|
||||
DAG.getConstant(VarArgsFrameOffset, MVT::i32));
|
||||
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
|
||||
return DAG.getStore(Op.getOperand(0), Offset,
|
||||
Op.getOperand(1), SV->getValue(), SV->getOffset());
|
||||
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
||||
return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
|
||||
}
|
||||
case ISD::VAARG: {
|
||||
SDNode *Node = Op.Val;
|
||||
MVT::ValueType VT = Node->getValueType(0);
|
||||
SDOperand InChain = Node->getOperand(0);
|
||||
SDOperand VAListPtr = Node->getOperand(1);
|
||||
SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
|
||||
SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
|
||||
SV->getValue(), SV->getOffset());
|
||||
const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
|
||||
SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, SV, 0);
|
||||
// Increment the pointer, VAList, to the next vaarg
|
||||
SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
|
||||
DAG.getConstant(MVT::getSizeInBits(VT)/8,
|
||||
getPointerTy()));
|
||||
// Store the incremented VAList to the legalized pointer
|
||||
InChain = DAG.getStore(VAList.getValue(1), NextPtr,
|
||||
VAListPtr, SV->getValue(), SV->getOffset());
|
||||
VAListPtr, SV, 0);
|
||||
// Load the actual argument out of the pointer VAList, unless this is an
|
||||
// f64 load.
|
||||
if (VT != MVT::f64) {
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/PseudoSourceValue.h"
|
||||
#include "llvm/CodeGen/SelectionDAG.h"
|
||||
#include "llvm/Support/MathExtras.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
|
|
@ -1088,7 +1089,8 @@ SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
|
|||
SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
|
||||
if (isByVal)
|
||||
return FIN;
|
||||
return DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0);
|
||||
return DAG.getLoad(VA.getValVT(), Root, FIN,
|
||||
&PseudoSourceValue::FPRel, FI);
|
||||
}
|
||||
|
||||
SDOperand
|
||||
|
|
@ -1216,7 +1218,9 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
|
|||
unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
|
||||
X86::GR64RegisterClass);
|
||||
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
|
||||
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
|
||||
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN,
|
||||
&PseudoSourceValue::FPRel,
|
||||
RegSaveFrameIndex);
|
||||
MemOps.push_back(Store);
|
||||
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
|
||||
DAG.getIntPtrConstant(8));
|
||||
|
|
@ -1229,7 +1233,9 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
|
|||
unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
|
||||
X86::VR128RegisterClass);
|
||||
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
|
||||
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
|
||||
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN,
|
||||
&PseudoSourceValue::FPRel,
|
||||
RegSaveFrameIndex);
|
||||
MemOps.push_back(Store);
|
||||
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
|
||||
DAG.getIntPtrConstant(16));
|
||||
|
|
@ -1558,7 +1564,8 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
|
|||
Flags, DAG));
|
||||
} else {
|
||||
// Store relative to framepointer.
|
||||
MemOpChains2.push_back(DAG.getStore(Chain, Source, FIN, NULL, 0));
|
||||
MemOpChains2.push_back(DAG.getStore(Chain, Source, FIN,
|
||||
&PseudoSourceValue::FPRel, FI));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -3784,7 +3791,8 @@ X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
|
|||
// the GV offset field. Platform check is inside GVRequiresExtraLoad() call
|
||||
// The same applies for external symbols during PIC codegen
|
||||
if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
|
||||
Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
|
||||
Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
|
||||
&PseudoSourceValue::GPRel, 0);
|
||||
|
||||
return Result;
|
||||
}
|
||||
|
|
@ -3842,7 +3850,8 @@ LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
|
|||
SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
|
||||
|
||||
if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
|
||||
Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, NULL, 0);
|
||||
Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
|
||||
&PseudoSourceValue::TPRel, 0);
|
||||
|
||||
// The address of the thread local variable is the add of the thread
|
||||
// pointer with the offset of the variable.
|
||||
|
|
@ -3974,7 +3983,7 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
|
|||
int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
|
||||
SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
||||
SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
|
||||
StackSlot, NULL, 0);
|
||||
StackSlot, &PseudoSourceValue::FPRel, SSFI);
|
||||
|
||||
// These are really Legal; caller falls through into that case.
|
||||
if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
|
||||
|
|
@ -4015,7 +4024,8 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
|
|||
Ops.push_back(DAG.getValueType(Op.getValueType()));
|
||||
Ops.push_back(InFlag);
|
||||
Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
|
||||
Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
|
||||
Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
|
||||
&PseudoSourceValue::FPRel, SSFI);
|
||||
}
|
||||
|
||||
return Result;
|
||||
|
|
@ -4053,7 +4063,8 @@ FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
|
|||
SDOperand Value = Op.getOperand(0);
|
||||
if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
|
||||
assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
|
||||
Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
|
||||
Chain = DAG.getStore(Chain, Value, StackSlot,
|
||||
&PseudoSourceValue::FPRel, SSFI);
|
||||
SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
|
||||
SDOperand Ops[] = {
|
||||
Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
|
||||
|
|
@ -4112,7 +4123,8 @@ SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
|
|||
}
|
||||
Constant *C = ConstantVector::get(CV);
|
||||
SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
|
||||
SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
|
||||
SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
|
||||
&PseudoSourceValue::CPRel, 0,
|
||||
false, 16);
|
||||
return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
|
||||
}
|
||||
|
|
@ -4140,7 +4152,8 @@ SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
|
|||
}
|
||||
Constant *C = ConstantVector::get(CV);
|
||||
SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
|
||||
SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
|
||||
SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
|
||||
&PseudoSourceValue::CPRel, 0,
|
||||
false, 16);
|
||||
if (MVT::isVector(VT)) {
|
||||
return DAG.getNode(ISD::BIT_CONVERT, VT,
|
||||
|
|
@ -4188,7 +4201,8 @@ SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
|
|||
}
|
||||
Constant *C = ConstantVector::get(CV);
|
||||
SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
|
||||
SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, NULL, 0,
|
||||
SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
|
||||
&PseudoSourceValue::CPRel, 0,
|
||||
false, 16);
|
||||
SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
|
||||
|
||||
|
|
@ -4216,7 +4230,8 @@ SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
|
|||
}
|
||||
C = ConstantVector::get(CV);
|
||||
CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
|
||||
SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
|
||||
SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
|
||||
&PseudoSourceValue::CPRel, 0,
|
||||
false, 16);
|
||||
SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
|
||||
|
||||
|
|
@ -4672,14 +4687,13 @@ SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
|
|||
}
|
||||
|
||||
SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
|
||||
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
|
||||
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
||||
|
||||
if (!Subtarget->is64Bit()) {
|
||||
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
||||
// memory location argument.
|
||||
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
|
||||
return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
|
||||
SV->getOffset());
|
||||
return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
|
||||
}
|
||||
|
||||
// __va_list_tag:
|
||||
|
|
@ -4692,28 +4706,26 @@ SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
|
|||
// Store gp_offset
|
||||
SDOperand Store = DAG.getStore(Op.getOperand(0),
|
||||
DAG.getConstant(VarArgsGPOffset, MVT::i32),
|
||||
FIN, SV->getValue(), SV->getOffset());
|
||||
FIN, SV, 0);
|
||||
MemOps.push_back(Store);
|
||||
|
||||
// Store fp_offset
|
||||
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
|
||||
Store = DAG.getStore(Op.getOperand(0),
|
||||
DAG.getConstant(VarArgsFPOffset, MVT::i32),
|
||||
FIN, SV->getValue(), SV->getOffset());
|
||||
FIN, SV, 0);
|
||||
MemOps.push_back(Store);
|
||||
|
||||
// Store ptr to overflow_arg_area
|
||||
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
|
||||
SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
|
||||
Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
|
||||
SV->getOffset());
|
||||
Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
|
||||
MemOps.push_back(Store);
|
||||
|
||||
// Store ptr to reg_save_area.
|
||||
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
|
||||
SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
|
||||
Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
|
||||
SV->getOffset());
|
||||
Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
|
||||
MemOps.push_back(Store);
|
||||
return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
|
||||
}
|
||||
|
|
@ -4723,18 +4735,15 @@ SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
|
|||
SDOperand Chain = Op.getOperand(0);
|
||||
SDOperand DstPtr = Op.getOperand(1);
|
||||
SDOperand SrcPtr = Op.getOperand(2);
|
||||
SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3));
|
||||
SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4));
|
||||
const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
|
||||
const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
|
||||
|
||||
SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
|
||||
SrcSV->getValue(), SrcSV->getOffset());
|
||||
SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr, SrcSV, 0);
|
||||
Chain = SrcPtr.getValue(1);
|
||||
for (unsigned i = 0; i < 3; ++i) {
|
||||
SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
|
||||
SrcSV->getValue(), SrcSV->getOffset());
|
||||
SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr, SrcSV, 0);
|
||||
Chain = Val.getValue(1);
|
||||
Chain = DAG.getStore(Chain, Val, DstPtr,
|
||||
DstSV->getValue(), DstSV->getOffset());
|
||||
Chain = DAG.getStore(Chain, Val, DstPtr, DstSV, 0);
|
||||
if (i == 2)
|
||||
break;
|
||||
SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
|
||||
|
|
@ -4914,7 +4923,7 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
|
|||
SDOperand FPtr = Op.getOperand(2); // nested function
|
||||
SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
|
||||
|
||||
SrcValueSDNode *TrmpSV = cast<SrcValueSDNode>(Op.getOperand(4));
|
||||
const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
|
||||
|
||||
const X86InstrInfo *TII =
|
||||
((X86TargetMachine&)getTargetMachine()).getInstrInfo();
|
||||
|
|
@ -4938,33 +4947,31 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
|
|||
unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
|
||||
SDOperand Addr = Trmp;
|
||||
OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
|
||||
TrmpSV->getValue(), TrmpSV->getOffset());
|
||||
TrmpAddr, 0);
|
||||
|
||||
Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
|
||||
OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpSV->getValue(),
|
||||
TrmpSV->getOffset() + 2, false, 2);
|
||||
OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
|
||||
|
||||
// Load the 'nest' parameter value into R10.
|
||||
// R10 is specified in X86CallingConv.td
|
||||
OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
|
||||
Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
|
||||
OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
|
||||
TrmpSV->getValue(), TrmpSV->getOffset() + 10);
|
||||
TrmpAddr, 10);
|
||||
|
||||
Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
|
||||
OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(),
|
||||
TrmpSV->getOffset() + 12, false, 2);
|
||||
OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
|
||||
|
||||
// Jump to the nested function.
|
||||
OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
|
||||
Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
|
||||
OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
|
||||
TrmpSV->getValue(), TrmpSV->getOffset() + 20);
|
||||
TrmpAddr, 20);
|
||||
|
||||
unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
|
||||
Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
|
||||
OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
|
||||
TrmpSV->getValue(), TrmpSV->getOffset() + 22);
|
||||
TrmpAddr, 22);
|
||||
|
||||
SDOperand Ops[] =
|
||||
{ Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
|
||||
|
|
@ -5022,20 +5029,18 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
|
|||
const unsigned char N86Reg =
|
||||
((X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg);
|
||||
OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
|
||||
Trmp, TrmpSV->getValue(), TrmpSV->getOffset());
|
||||
Trmp, TrmpAddr, 0);
|
||||
|
||||
Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
|
||||
OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(),
|
||||
TrmpSV->getOffset() + 1, false, 1);
|
||||
OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
|
||||
|
||||
const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
|
||||
Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
|
||||
OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
|
||||
TrmpSV->getValue() + 5, TrmpSV->getOffset());
|
||||
TrmpAddr, 5, false, 1);
|
||||
|
||||
Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
|
||||
OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpSV->getValue(),
|
||||
TrmpSV->getOffset() + 6, false, 1);
|
||||
OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
|
||||
|
||||
SDOperand Ops[] =
|
||||
{ Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
|
||||
|
|
|
|||
|
|
@ -311,6 +311,12 @@ private:
|
|||
std::vector<std::pair<std::string, std::string> > OrigChains;
|
||||
std::set<std::string> Duplicates;
|
||||
|
||||
/// LSI - Load/Store information.
|
||||
/// Save loads/stores matched by a pattern, and generate a MemOperandSDNode
|
||||
/// for each memory access. This facilitates the use of AliasAnalysis in
|
||||
/// the backend.
|
||||
std::vector<std::string> LSI;
|
||||
|
||||
/// GeneratedCode - This is the buffer that we emit code to. The first int
|
||||
/// indicates whether this is an exit predicate (something that should be
|
||||
/// tested, and if true, the match fails) [when 1], or normal code to emit
|
||||
|
|
@ -371,6 +377,15 @@ public:
|
|||
void EmitMatchCode(TreePatternNode *N, TreePatternNode *P,
|
||||
const std::string &RootName, const std::string &ChainSuffix,
|
||||
bool &FoundChain) {
|
||||
|
||||
// Save loads/stores matched by a pattern.
|
||||
if (!N->isLeaf() && N->getName().empty() &&
|
||||
((N->getOperator()->getName() == "ld") ||
|
||||
(N->getOperator()->getName() == "st") ||
|
||||
(N->getOperator()->getName() == "ist"))) {
|
||||
LSI.push_back(RootName);
|
||||
}
|
||||
|
||||
bool isRoot = (P == NULL);
|
||||
// Emit instruction predicates. Each predicate is just a string for now.
|
||||
if (isRoot) {
|
||||
|
|
@ -927,6 +942,18 @@ public:
|
|||
}
|
||||
}
|
||||
|
||||
// Generate MemOperandSDNodes nodes for each memory accesses covered by this
|
||||
// pattern.
|
||||
if (isRoot) {
|
||||
std::vector<std::string>::const_iterator mi, mie;
|
||||
for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) {
|
||||
emitCode("SDOperand LSI_" + *mi + " = "
|
||||
"CurDAG->getMemOperand(cast<LSBaseSDNode>(" +
|
||||
*mi + ")->getMemOperand());");
|
||||
AllOps.push_back("LSI_" + *mi);
|
||||
}
|
||||
}
|
||||
|
||||
// Emit all the chain and CopyToReg stuff.
|
||||
bool ChainEmitted = NodeHasChain;
|
||||
if (NodeHasChain)
|
||||
|
|
|
|||
Loading…
Reference in New Issue