forked from OSchip/llvm-project
* Set the low bit of the return address when we are in thumb mode.
* Some code cleanup. llvm-svn: 141317
This commit is contained in:
Bill Wendling
parent
ceb4c7523f
commit
362c1b01cc
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@ -5512,79 +5512,8 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
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const TargetRegisterClass *TRC =
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isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
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MachineMemOperand *CPMMO =
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MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
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MachineMemOperand::MOLoad, 4, 4);
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MachineMemOperand *FIMMO =
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MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOStore, 4, 4);
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// Load the address of the dispatch MBB into the jump buffer.
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if (isThumb2) {
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// Incoming value: jbuf
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// ldr.n r1, LCPI1_4
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// add r1, pc
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// str r5, [$jbuf, #+4] ; &jbuf[1]
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unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
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.addConstantPoolIndex(CPI)
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.addMemOperand(CPMMO));
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unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
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BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
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.addReg(NewVReg1, RegState::Kill)
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.addImm(PCLabelId);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
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.addReg(NewVReg2, RegState::Kill)
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.addFrameIndex(FI)
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.addImm(36) // &jbuf[1] :: pc
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.addMemOperand(FIMMO));
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} else if (isThumb) {
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// Incoming value: jbuf
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// ldr.n r1, LCPI1_4
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// add r1, pc
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// add r2, $jbuf, #+4 ; &jbuf[1]
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// str r1, [r2]
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unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
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.addConstantPoolIndex(CPI)
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.addMemOperand(CPMMO));
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unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
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BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
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.addReg(NewVReg1)
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.addImm(PCLabelId);
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unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg3)
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.addFrameIndex(FI)
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.addImm(36)); // &jbuf[1] :: pc
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
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.addReg(NewVReg2, RegState::Kill)
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.addReg(NewVReg3, RegState::Kill)
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.addImm(0)
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.addMemOperand(FIMMO));
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} else {
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// Incoming value: jbuf
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// ldr r1, LCPI1_1
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// add r1, pc, r1
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// str r1, [$jbuf, #+4] ; &jbuf[1]
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unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
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.addConstantPoolIndex(CPI)
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.addImm(0)
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.addMemOperand(CPMMO));
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unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
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.addReg(NewVReg1, RegState::Kill)
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.addImm(PCLabelId));
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
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.addReg(NewVReg2, RegState::Kill)
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.addFrameIndex(FI)
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.addImm(36) // &jbuf[1] :: pc
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.addMemOperand(FIMMO));
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}
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// Now get a mapping of the call site numbers to all of the landing pads
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// they're associated with.
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// Get a mapping of the call site numbers to all of the landing pads they're
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// associated with.
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DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
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unsigned MaxCSNum = 0;
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MachineModuleInfo &MMI = MF->getMMI();
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@ -5624,11 +5553,13 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
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assert(!LPadList.empty() &&
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"No landing pad destinations for the dispatch jump table!");
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// Create the jump table and associated information.
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MachineJumpTableInfo *JTI =
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MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
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unsigned MJTI = JTI->createJumpTableIndex(LPadList);
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unsigned UId = AFI->createJumpTableUId();
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// Create the MBBs for the dispatch code.
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MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
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BuildMI(TrapBB, dl, TII->get(ARM::TRAP));
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DispatchBB->addSuccessor(TrapBB);
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@ -5643,6 +5574,92 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
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MF->insert(MF->end(), TrapBB);
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MF->RenumberBlocks(Last);
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// Grab constant pool and fixed stack memory operands.
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MachineMemOperand *CPMMO =
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MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
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MachineMemOperand::MOLoad, 4, 4);
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MachineMemOperand *FIMMO =
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MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOStore, 4, 4);
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// Load the address of the dispatch MBB into the jump buffer.
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if (isThumb2) {
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// Incoming value: jbuf
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// ldr.n r5, LCPI1_1
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// orr r5, r5, #1
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// add r5, pc
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// str r5, [$jbuf, #+4] ; &jbuf[1]
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unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
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.addConstantPoolIndex(CPI)
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.addMemOperand(CPMMO));
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// Set the low bit because of thumb mode.
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unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
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AddDefaultCC(
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
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.addReg(NewVReg1, RegState::Kill)
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.addImm(0x01)));
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unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
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BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
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.addReg(NewVReg2, RegState::Kill)
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.addImm(PCLabelId);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
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.addReg(NewVReg3, RegState::Kill)
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.addFrameIndex(FI)
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.addImm(36) // &jbuf[1] :: pc
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.addMemOperand(FIMMO));
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} else if (isThumb) {
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// Incoming value: jbuf
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// ldr.n r1, LCPI1_4
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// add r1, pc
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// orr r1, r1, #1
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// add r2, $jbuf, #+4 ; &jbuf[1]
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// str r1, [r2]
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unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
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.addConstantPoolIndex(CPI)
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.addMemOperand(CPMMO));
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unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
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BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
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.addReg(NewVReg1, RegState::Kill)
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.addImm(PCLabelId);
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// Set the low bit because of thumb mode.
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unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
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AddDefaultCC(
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg3)
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.addReg(NewVReg2, RegState::Kill)
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.addImm(0x01)));
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unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg4)
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.addFrameIndex(FI)
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.addImm(36)); // &jbuf[1] :: pc
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
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.addReg(NewVReg3, RegState::Kill)
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.addReg(NewVReg4, RegState::Kill)
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.addImm(0)
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.addMemOperand(FIMMO));
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} else {
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// Incoming value: jbuf
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// ldr r1, LCPI1_1
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// add r1, pc, r1
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// str r1, [$jbuf, #+4] ; &jbuf[1]
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unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
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.addConstantPoolIndex(CPI)
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.addImm(0)
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.addMemOperand(CPMMO));
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unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
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.addReg(NewVReg1, RegState::Kill)
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.addImm(PCLabelId));
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
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.addReg(NewVReg2, RegState::Kill)
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.addFrameIndex(FI)
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.addImm(36) // &jbuf[1] :: pc
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.addMemOperand(FIMMO));
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}
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FIMMO = MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOLoad, 4, 4);
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