forked from OSchip/llvm-project
AMDGPU/GlobalISel: Handle sbfe/ubfe intrinsic
Try to handle arbitrary scalar BFEs by packing the operands. The DAG gives up on non-constant arguments. We're still missing any constant folding, so we end up with pretty ugly code most of the time. Also handle the 64-bit scalar case, which the DAG doesn't try to do.
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
323db5d666
commit
361f2a7818
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@ -278,8 +278,8 @@ def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
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def AMDGPUround : SDNode<"ISD::FROUND",
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
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def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfe_u32_impl : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfe_i32_impl : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
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@ -460,3 +460,11 @@ def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),
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def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
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[(int_amdgcn_mul_i24 node:$src0, node:$src1),
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(AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
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def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
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[(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
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(AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;
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def AMDGPUbfe_u32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
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[(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
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(AMDGPUbfe_u32_impl node:$src0, node:$src1, node:$src2)]>;
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@ -160,8 +160,9 @@ public:
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if (!Op.isReg())
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continue;
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// We may see physical registers if building a real MI
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Register Reg = Op.getReg();
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if (MRI.getRegClassOrRegBank(Reg))
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if (Reg.isPhysical() || MRI.getRegClassOrRegBank(Reg))
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continue;
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const RegisterBank *RB = NewBank;
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@ -1444,6 +1445,65 @@ bool AMDGPURegisterBankInfo::applyMappingSBufferLoad(
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return true;
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}
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bool AMDGPURegisterBankInfo::applyMappingBFEIntrinsic(
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const OperandsMapper &OpdMapper, bool Signed) const {
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MachineInstr &MI = OpdMapper.getMI();
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MachineRegisterInfo &MRI = OpdMapper.getMRI();
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// Insert basic copies
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applyDefaultMapping(OpdMapper);
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Register DstReg = MI.getOperand(0).getReg();
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LLT Ty = MRI.getType(DstReg);
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const LLT S32 = LLT::scalar(32);
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const RegisterBank *DstBank =
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OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
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if (DstBank == &AMDGPU::VGPRRegBank) {
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if (Ty == S32)
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return true;
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// TODO: 64-bit version is scalar only, so we need to expand this.
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return false;
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}
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Register SrcReg = MI.getOperand(2).getReg();
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Register OffsetReg = MI.getOperand(3).getReg();
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Register WidthReg = MI.getOperand(4).getReg();
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// The scalar form packs the offset and width in a single operand.
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ApplyRegBankMapping ApplyBank(*this, MRI, &AMDGPU::SGPRRegBank);
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GISelObserverWrapper Observer(&ApplyBank);
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MachineIRBuilder B(MI);
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B.setChangeObserver(Observer);
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// Ensure the high bits are clear to insert the offset.
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auto OffsetMask = B.buildConstant(S32, maskTrailingOnes<unsigned>(6));
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auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask);
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// Zeros out the low bits, so don't bother clamping the input value.
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auto ShiftWidth = B.buildShl(S32, WidthReg, B.buildConstant(S32, 16));
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// Transformation function, pack the offset and width of a BFE into
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// the format expected by the S_BFE_I32 / S_BFE_U32. In the second
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// source, bits [5:0] contain the offset and bits [22:16] the width.
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auto MergedInputs = B.buildOr(S32, ClampOffset, ShiftWidth);
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// TODO: It might be worth using a pseudo here to avoid scc clobber and
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// register class constraints.
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unsigned Opc = Ty == S32 ? (Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32) :
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(Signed ? AMDGPU::S_BFE_I64 : AMDGPU::S_BFE_U64);
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auto MIB = B.buildInstr(Opc, {DstReg}, {SrcReg, MergedInputs});
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if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this))
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llvm_unreachable("failed to constrain BFE");
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MI.eraseFromParent();
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return true;
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}
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// FIXME: Duplicated from LegalizerHelper
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static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
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switch (Opc) {
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@ -2592,8 +2652,12 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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constrainOpWithReadfirstlane(MI, MRI, 5);
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return;
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}
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default:
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break;
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case Intrinsic::amdgcn_sbfe:
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applyMappingBFEIntrinsic(OpdMapper, true);
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return;
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case Intrinsic::amdgcn_ubfe:
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applyMappingBFEIntrinsic(OpdMapper, false);
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return;
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}
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break;
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}
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@ -2687,7 +2751,11 @@ AMDGPURegisterBankInfo::getDefaultMappingSOP(const MachineInstr &MI) const {
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SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
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const MachineOperand &SrcOp = MI.getOperand(i);
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if (!SrcOp.isReg())
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continue;
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unsigned Size = getSizeInBits(SrcOp.getReg(), MRI, *TRI);
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OpdsMapping[i] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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}
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return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
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@ -3498,8 +3566,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case Intrinsic::amdgcn_fmad_ftz:
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case Intrinsic::amdgcn_mbcnt_lo:
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case Intrinsic::amdgcn_mbcnt_hi:
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case Intrinsic::amdgcn_ubfe:
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case Intrinsic::amdgcn_sbfe:
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case Intrinsic::amdgcn_mul_u24:
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case Intrinsic::amdgcn_mul_i24:
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case Intrinsic::amdgcn_lerp:
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@ -3521,6 +3587,11 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case Intrinsic::amdgcn_sdot8:
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case Intrinsic::amdgcn_udot8:
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return getDefaultMappingVOP(MI);
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case Intrinsic::amdgcn_sbfe:
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case Intrinsic::amdgcn_ubfe:
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if (isSALUMapping(MI))
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return getDefaultMappingSOP(MI);
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return getDefaultMappingVOP(MI);
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case Intrinsic::amdgcn_ds_swizzle:
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case Intrinsic::amdgcn_ds_permute:
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case Intrinsic::amdgcn_ds_bpermute:
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@ -78,6 +78,9 @@ public:
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MachineRegisterInfo &MRI, int RSrcIdx) const;
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bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const;
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bool applyMappingBFEIntrinsic(const OperandsMapper &OpdMapper,
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bool Signed) const;
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void lowerScalarMinMax(MachineIRBuilder &B, MachineInstr &MI) const;
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Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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@ -0,0 +1,962 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -amdgpu-load-store-vectorizer=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6 %s
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define i32 @v_bfe_i32_arg_arg_arg(i32 %src0, i32 %src1, i32 %src2) #0 {
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; GFX6-LABEL: v_bfe_i32_arg_arg_arg:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: v_bfe_i32 v0, v0, v1, v2
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 %src1, i32 %src2)
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ret i32 %bfe_i32
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}
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define amdgpu_ps i32 @s_bfe_i32_arg_arg_arg(i32 inreg %src0, i32 inreg %src1, i32 inreg %src2) #0 {
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; GFX6-LABEL: s_bfe_i32_arg_arg_arg:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_and_b32 s1, s1, 63
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; GFX6-NEXT: s_lshl_b32 s2, s2, 16
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; GFX6-NEXT: s_or_b32 s1, s1, s2
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; GFX6-NEXT: s_bfe_i32 s0, s0, s1
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; GFX6-NEXT: ; return to shader part epilog
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%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 %src1, i32 %src2)
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ret i32 %bfe_i32
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}
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; TODO: Need to expand this
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; define i64 @v_bfe_i64_arg_arg_arg(i64 %src0, i32 %src1, i32 %src2) #0 {
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; %bfe_i64 = call i32 @llvm.amdgcn.sbfe.i64(i32 %src0, i32 %src1, i32 %src2)
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; ret i64 %bfe_i64
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; }
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define amdgpu_ps i64 @s_bfe_i64_arg_arg_arg(i64 inreg %src0, i32 inreg %src1, i32 inreg %src2) #0 {
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; GFX6-LABEL: s_bfe_i64_arg_arg_arg:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_and_b32 s2, s2, 63
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; GFX6-NEXT: s_lshl_b32 s3, s3, 16
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; GFX6-NEXT: s_or_b32 s2, s2, s3
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; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], s2
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; GFX6-NEXT: ; return to shader part epilog
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%bfe_i32 = call i64 @llvm.amdgcn.sbfe.i64(i64 %src0, i32 %src1, i32 %src2)
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ret i64 %bfe_i32
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}
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define amdgpu_kernel void @bfe_i32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #0 {
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; GFX6-LABEL: bfe_i32_arg_arg_imm:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; GFX6-NEXT: s_load_dword s2, s[0:1], 0xb
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; GFX6-NEXT: s_load_dword s0, s[0:1], 0xc
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; GFX6-NEXT: s_mov_b32 s6, -1
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_and_b32 s0, s0, 63
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; GFX6-NEXT: s_or_b32 s0, s0, 0x7b0000
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; GFX6-NEXT: s_bfe_i32 s0, s2, s0
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; GFX6-NEXT: v_mov_b32_e32 v0, s0
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; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GFX6-NEXT: s_endpgm
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%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 %src1, i32 123)
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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define amdgpu_kernel void @bfe_i32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) #0 {
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; GFX6-LABEL: bfe_i32_arg_imm_arg:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; GFX6-NEXT: s_load_dword s2, s[0:1], 0xb
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; GFX6-NEXT: s_load_dword s0, s[0:1], 0xc
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; GFX6-NEXT: s_mov_b32 s6, -1
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_lshl_b32 s0, s0, 16
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; GFX6-NEXT: s_or_b32 s0, 59, s0
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; GFX6-NEXT: s_bfe_i32 s0, s2, s0
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; GFX6-NEXT: v_mov_b32_e32 v0, s0
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; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GFX6-NEXT: s_endpgm
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%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 123, i32 %src2)
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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define amdgpu_kernel void @bfe_i32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) #0 {
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; GFX6-LABEL: bfe_i32_imm_arg_arg:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; GFX6-NEXT: s_load_dword s2, s[0:1], 0xb
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; GFX6-NEXT: s_load_dword s0, s[0:1], 0xc
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; GFX6-NEXT: s_mov_b32 s6, -1
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_and_b32 s1, s2, 63
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; GFX6-NEXT: s_lshl_b32 s0, s0, 16
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; GFX6-NEXT: s_or_b32 s0, s1, s0
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; GFX6-NEXT: s_bfe_i32 s0, 0x7b, s0
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; GFX6-NEXT: v_mov_b32_e32 v0, s0
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; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GFX6-NEXT: s_endpgm
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%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 123, i32 %src1, i32 %src2)
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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define amdgpu_kernel void @v_bfe_print_arg(i32 addrspace(1)* %out, i32 addrspace(1)* %src0) #0 {
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; GFX6-LABEL: v_bfe_print_arg:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
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; GFX6-NEXT: s_mov_b32 s6, -1
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_bfe_i32 s0, s0, 0x80002
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; GFX6-NEXT: v_mov_b32_e32 v0, s0
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; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GFX6-NEXT: s_endpgm
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%load = load i32, i32 addrspace(1)* %src0, align 4
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%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 2, i32 8)
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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define amdgpu_kernel void @bfe_i32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #0 {
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; GFX6-LABEL: bfe_i32_arg_0_width_reg_offset:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; GFX6-NEXT: s_load_dword s2, s[0:1], 0xb
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; GFX6-NEXT: s_load_dword s0, s[0:1], 0xc
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; GFX6-NEXT: s_mov_b32 s6, -1
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_and_b32 s0, s0, 63
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; GFX6-NEXT: s_bfe_i32 s0, s2, s0
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; GFX6-NEXT: v_mov_b32_e32 v0, s0
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; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GFX6-NEXT: s_endpgm
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%bfe_u32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 %src1, i32 0)
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store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
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ret void
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}
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define amdgpu_kernel void @bfe_i32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #0 {
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; GFX6-LABEL: bfe_i32_arg_0_width_imm_offset:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
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; GFX6-NEXT: s_mov_b32 s6, -1
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_bfe_i32 s0, s0, 8
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; GFX6-NEXT: v_mov_b32_e32 v0, s0
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; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GFX6-NEXT: s_endpgm
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%bfe_u32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 8, i32 0)
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; GFX6-LABEL: bfe_i32_test_6:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_lshl_b32 s0, s0, 31
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x1f0001
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 31
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shl, i32 1, i32 31)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; GFX6-LABEL: bfe_i32_test_7:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_lshl_b32 s0, s0, 31
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x1f0000
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 31
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shl, i32 0, i32 31)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; GFX6-LABEL: bfe_i32_test_8:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_lshl_b32 s0, s0, 31
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x1001f
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 31
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shl, i32 31, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; GFX6-LABEL: bfe_i32_test_9:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x1001f
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %x, i32 31, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; GFX6-LABEL: bfe_i32_test_10:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x1f0001
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %x, i32 1, i32 31)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; GFX6-LABEL: bfe_i32_test_11:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x180008
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %x, i32 8, i32 24)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; GFX6-LABEL: bfe_i32_test_12:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x80018
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %x, i32 24, i32 8)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; GFX6-LABEL: bfe_i32_test_13:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_ashr_i32 s0, s0, 31
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x1001f
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = ashr i32 %x, 31
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shl, i32 31, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; GFX6-LABEL: bfe_i32_test_14:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_lshr_b32 s0, s0, 31
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x1001f
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = lshr i32 %x, 31
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shl, i32 31, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_0(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_0:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0, 0
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 0, i32 0, i32 0)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_1(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_1:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0x302e, 0
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 12334, i32 0, i32 0)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_2(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_2:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0, 0x10000
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 0, i32 0, i32 1)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_3(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_3:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 1, 0x10000
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 1, i32 0, i32 1)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_4(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_4:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_bfe_i32 s3, -1, 0x10000
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s3
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 4294967295, i32 0, i32 1)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_5(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_5:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_mov_b32 s2, 0x10007
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0x80, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 128, i32 7, i32 1)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_6(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_6:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_mov_b32 s2, 0x80000
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0x80, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 128, i32 0, i32 8)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_7(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_7:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_mov_b32 s2, 0x80000
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0x7f, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 127, i32 0, i32 8)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_8(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_8:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_mov_b32 s2, 0x80006
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0x7f, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 127, i32 6, i32 8)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_9(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_9:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_mov_b32 s2, 0x80010
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0x10000, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 65536, i32 16, i32 8)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_10(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_10:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_mov_b32 s2, 0x100010
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0xffff, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 65535, i32 16, i32 16)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_11(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_11:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_mov_b32 s2, 0x40004
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0xa0, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 160, i32 4, i32 4)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_12(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_12:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_mov_b32 s2, 0x1001f
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0xa0, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 160, i32 31, i32 1)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_13(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_13:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_mov_b32 s2, 0x100010
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0x1fffe, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 131070, i32 16, i32 16)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_14(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_14:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_mov_b32 s2, 0x1e0002
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0xa0, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 160, i32 2, i32 30)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_15(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_15:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_mov_b32 s2, 0x1c0004
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0xa0, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 160, i32 4, i32 28)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_16(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_16:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_bfe_i32 s3, -1, 0x70001
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s3
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 4294967295, i32 1, i32 7)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_17(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_17:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_mov_b32 s2, 0x1f0001
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0xff, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 255, i32 1, i32 31)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_18(i32 addrspace(1)* %out) #0 {
|
||||
; GFX6-LABEL: bfe_i32_constant_fold_test_18:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_mov_b32 s2, 0x1001f
|
||||
; GFX6-NEXT: s_bfe_i32 s2, 0xff, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 255, i32 31, i32 1)
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; GFX6-LABEL: bfe_sext_in_reg_i24:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x180000
|
||||
; GFX6-NEXT: s_lshl_b32 s0, s0, 8
|
||||
; GFX6-NEXT: s_ashr_i32 s0, s0, 8
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %x, i32 0, i32 24)
|
||||
%shl = shl i32 %bfe, 8
|
||||
%ashr = ashr i32 %shl, 8
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME
|
||||
; define amdgpu_kernel void @simplify_demanded_bfe_sdiv(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; %src = load i32, i32 addrspace(1)* %in, align 4
|
||||
; %bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %src, i32 1, i32 16)
|
||||
; %div = sdiv i32 %bfe, 2
|
||||
; store i32 %div, i32 addrspace(1)* %out, align 4
|
||||
; ret void
|
||||
; }
|
||||
|
||||
define amdgpu_kernel void @bfe_0_width(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
|
||||
; GFX6-LABEL: bfe_0_width:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 8
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%load = load i32, i32 addrspace(1)* %ptr, align 4
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 8, i32 0)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_8_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
|
||||
; GFX6-LABEL: bfe_8_bfe_8:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_mov_b32 s1, 0x80000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, s1
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, s1
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%load = load i32, i32 addrspace(1)* %ptr, align 4
|
||||
%bfe0 = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 0, i32 8)
|
||||
%bfe1 = call i32 @llvm.amdgcn.sbfe.i32(i32 %bfe0, i32 0, i32 8)
|
||||
store i32 %bfe1, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_8_bfe_16(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
|
||||
; GFX6-LABEL: bfe_8_bfe_16:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x80000
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x100000
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%load = load i32, i32 addrspace(1)* %ptr, align 4
|
||||
%bfe0 = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 0, i32 8)
|
||||
%bfe1 = call i32 @llvm.amdgcn.sbfe.i32(i32 %bfe0, i32 0, i32 16)
|
||||
store i32 %bfe1, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; This really should be folded into 1
|
||||
define amdgpu_kernel void @bfe_16_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
|
||||
; GFX6-LABEL: bfe_16_bfe_8:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x100000
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x80000
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%load = load i32, i32 addrspace(1)* %ptr, align 4
|
||||
%bfe0 = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 0, i32 16)
|
||||
%bfe1 = call i32 @llvm.amdgcn.sbfe.i32(i32 %bfe0, i32 0, i32 8)
|
||||
store i32 %bfe1, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Make sure there isn't a redundant BFE
|
||||
define amdgpu_kernel void @sext_in_reg_i8_to_i32_bfe(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
||||
; GFX6-LABEL: sext_in_reg_i8_to_i32_bfe:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dword s2, s[0:1], 0xb
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0xc
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_add_i32 s2, s2, s0
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s2, 0x80000
|
||||
; GFX6-NEXT: s_lshl_b32 s0, s0, 24
|
||||
; GFX6-NEXT: s_ashr_i32 s0, s0, 24
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%c = add i32 %a, %b ; add to prevent folding into extload
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %c, i32 0, i32 8)
|
||||
%shl = shl i32 %bfe, 24
|
||||
%ashr = ashr i32 %shl, 24
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sext_in_reg_i8_to_i32_bfe_wrong(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
||||
; GFX6-LABEL: sext_in_reg_i8_to_i32_bfe_wrong:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dword s2, s[0:1], 0xb
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0xc
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_add_i32 s2, s2, s0
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s2, 8
|
||||
; GFX6-NEXT: s_lshl_b32 s0, s0, 24
|
||||
; GFX6-NEXT: s_ashr_i32 s0, s0, 24
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%c = add i32 %a, %b ; add to prevent folding into extload
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %c, i32 8, i32 0)
|
||||
%shl = shl i32 %bfe, 24
|
||||
%ashr = ashr i32 %shl, 24
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sextload_i8_to_i32_bfe(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) #0 {
|
||||
; GFX6-LABEL: sextload_i8_to_i32_bfe:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_mov_b64 s[6:7], s[2:3]
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_load_sbyte v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
|
||||
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%load = load i8, i8 addrspace(1)* %ptr, align 1
|
||||
%sext = sext i8 %load to i32
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %sext, i32 0, i32 8)
|
||||
%shl = shl i32 %bfe, 24
|
||||
%ashr = ashr i32 %shl, 24
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sextload_i8_to_i32_bfe_0(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) #0 {
|
||||
; GFX6-LABEL: sextload_i8_to_i32_bfe_0:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX6-NEXT: s_mov_b64 s[6:7], s[2:3]
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: buffer_load_sbyte v0, off, s[0:3], 0
|
||||
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX6-NEXT: v_bfe_i32 v0, v0, 8, 0
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
|
||||
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%load = load i8, i8 addrspace(1)* %ptr, align 1
|
||||
%sext = sext i8 %load to i32
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %sext, i32 8, i32 0)
|
||||
%shl = shl i32 %bfe, 24
|
||||
%ashr = ashr i32 %shl, 24
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sext_in_reg_i1_bfe_offset_0(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; GFX6-LABEL: sext_in_reg_i1_bfe_offset_0:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_lshl_b32 s0, s0, 31
|
||||
; GFX6-NEXT: s_ashr_i32 s0, s0, 31
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x10000
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 31
|
||||
%shr = ashr i32 %shl, 31
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shr, i32 0, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sext_in_reg_i1_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; GFX6-LABEL: sext_in_reg_i1_bfe_offset_1:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_lshl_b32 s0, s0, 30
|
||||
; GFX6-NEXT: s_ashr_i32 s0, s0, 30
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x10001
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 30
|
||||
%shr = ashr i32 %shl, 30
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shr, i32 1, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sext_in_reg_i2_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
; GFX6-LABEL: sext_in_reg_i2_bfe_offset_1:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
|
||||
; GFX6-NEXT: s_mov_b32 s6, -1
|
||||
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_lshl_b32 s0, s0, 30
|
||||
; GFX6-NEXT: s_ashr_i32 s0, s0, 30
|
||||
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x20001
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GFX6-NEXT: s_endpgm
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 30
|
||||
%shr = ashr i32 %shl, 30
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shr, i32 1, i32 2)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.amdgcn.sbfe.i32(i32, i32, i32) #1
|
||||
declare i64 @llvm.amdgcn.sbfe.i64(i64, i32, i32) #1
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readnone }
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue