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AArch64: Don't emit CFI for SCS register in nounwind functions. 

All that you can legitimately do with the CFI for a nounwind function
is get a backtrace, and adjusting the SCS register is not (currently)
required for this purpose.

Differential Revision: https://reviews.llvm.org/D54988

llvm-svn: 348035
This commit is contained in:
Peter Collingbourne 2018-11-30 21:04:25 +00:00
parent 58e94f91a8
commit 35fcc294ab
2 changed files with 24 additions and 14 deletions
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30
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
View File

@ -1733,20 +1733,22 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
BuildMI(MBB, MI, DL, TII.get(AArch64::SEH_Nop)) BuildMI(MBB, MI, DL, TII.get(AArch64::SEH_Nop))
.setMIFlag(MachineInstr::FrameSetup); .setMIFlag(MachineInstr::FrameSetup);
// Emit a CFI instruction that causes 8 to be subtracted from the value of if (!MF.getFunction().hasFnAttribute(Attribute::NoUnwind)) {
// x18 when unwinding past this frame. // Emit a CFI instruction that causes 8 to be subtracted from the value of
static const char CFIInst[] = { // x18 when unwinding past this frame.
dwarf::DW_CFA_val_expression, static const char CFIInst[] = {
18, // register dwarf::DW_CFA_val_expression,
2, // length 18, // register
static_cast<char>(unsigned(dwarf::DW_OP_breg18)), 2, // length
static_cast<char>(-8) & 0x7f, // addend (sleb128) static_cast<char>(unsigned(dwarf::DW_OP_breg18)),
}; static_cast<char>(-8) & 0x7f, // addend (sleb128)
unsigned CFIIndex = };
MF.addFrameInst(MCCFIInstruction::createEscape(nullptr, CFIInst)); unsigned CFIIndex =
BuildMI(MBB, MI, DL, TII.get(AArch64::CFI_INSTRUCTION)) MF.addFrameInst(MCCFIInstruction::createEscape(nullptr, CFIInst));
.addCFIIndex(CFIIndex) BuildMI(MBB, MI, DL, TII.get(AArch64::CFI_INSTRUCTION))
.setMIFlag(MachineInstr::FrameSetup); .addCFIIndex(CFIIndex)
.setMIFlag(MachineInstr::FrameSetup);
}
// This instruction also makes x18 live-in to the entry block. // This instruction also makes x18 live-in to the entry block.
MBB.addLiveIn(AArch64::X18); MBB.addLiveIn(AArch64::X18);

8
llvm/test/CodeGen/AArch64/shadow-call-stack.ll
View File

@ -46,3 +46,11 @@ define i32 @f4() shadowcallstack {
; CHECK: ret ; CHECK: ret
ret i32 %res1234 ret i32 %res1234
} }
define i32 @f5() shadowcallstack nounwind {
; CHECK: f5:
; CHECK-NOT: .cfi_escape
%res = call i32 @bar()
%res1 = add i32 %res, 1
ret i32 %res
}