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[ARM GlobalISel] Support floating point for Thumb2 

This is exactly the same as arm mode, so for the instruction selector
tests we just extract them to a new file and run with the same checks
for both arm and thumb mode.

For the legalizer we need to update the tests for soft float a bit, but
only because BL and tBL are slightly different. We could be pedantic and
check that we get a well-formed BL for arm mode and a tBL for thumb, but
for the purposes of the legalizer test it's sufficient to just skip over
the predicate operands in the checks. Also note that we have the
pedantic checks in the divmod test, so we're covered.

llvm-svn: 354665
This commit is contained in:
Diana Picus 2019-02-22 09:54:54 +00:00
parent c8f7496257
commit 35e1c6663c
4 changed files with 1025 additions and 997 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

58
llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
View File

@ -149,35 +149,6 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
getActionDefinitionsBuilder(G_BRCOND).legalFor({s1});
if (ST.isThumb()) {
// FIXME: merge with the code for non-Thumb.
computeTables();
verify(*ST.getInstrInfo());
return;
}
getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0});
if (ST.hasV5TOps()) {
getActionDefinitionsBuilder(G_CTLZ)
.legalFor({s32, s32})
.clampScalar(1, s32, s32)
.clampScalar(0, s32, s32);
getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
.lowerFor({s32, s32})
.clampScalar(1, s32, s32)
.clampScalar(0, s32, s32);
} else {
getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
.libcallFor({s32, s32})
.clampScalar(1, s32, s32)
.clampScalar(0, s32, s32);
getActionDefinitionsBuilder(G_CTLZ)
.lowerFor({s32, s32})
.clampScalar(1, s32, s32)
.clampScalar(0, s32, s32);
}
if (!ST.useSoftFloat() && ST.hasVFP2()) {
getActionDefinitionsBuilder(
{G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
@ -234,6 +205,35 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
if (ST.isThumb()) {
// FIXME: merge with the code for non-Thumb.
computeTables();
verify(*ST.getInstrInfo());
return;
}
getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0});
if (ST.hasV5TOps()) {
getActionDefinitionsBuilder(G_CTLZ)
.legalFor({s32, s32})
.clampScalar(1, s32, s32)
.clampScalar(0, s32, s32);
getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
.lowerFor({s32, s32})
.clampScalar(1, s32, s32)
.clampScalar(0, s32, s32);
} else {
getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
.libcallFor({s32, s32})
.clampScalar(1, s32, s32)
.clampScalar(0, s32, s32);
getActionDefinitionsBuilder(G_CTLZ)
.lowerFor({s32, s32})
.clampScalar(1, s32, s32)
.clampScalar(0, s32, s32);
}
computeTables();
verify(*ST.getInstrInfo());
}

866
llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
View File

@ -6,66 +6,32 @@
define void @test_trunc_and_zext_s16() { ret void }
define void @test_trunc_and_anyext_s8() { ret void }
define void @test_trunc_and_anyext_s16() { ret void }
define void @test_trunc_s64() #0 { ret void }
define void @test_add_s32() { ret void }
define void @test_add_fold_imm_s32() { ret void }
define void @test_add_no_fold_imm_s32() #3 { ret void }
define void @test_fadd_s32() #0 { ret void }
define void @test_fadd_s64() #0 { ret void }
define void @test_fsub_s32() #0 { ret void }
define void @test_fsub_s64() #0 { ret void }
define void @test_fmul_s32() #0 { ret void }
define void @test_fmul_s64() #0 { ret void }
define void @test_fdiv_s32() #0 { ret void }
define void @test_fdiv_s64() #0 { ret void }
define void @test_fneg_s32() #0 { ret void }
define void @test_fneg_s64() #0 { ret void }
define void @test_fma_s32() #4 { ret void }
define void @test_fma_s64() #4 { ret void }
define void @test_fpext_s32_to_s64() #0 { ret void }
define void @test_fptrunc_s64_to_s32() #0 {ret void }
define void @test_fptosi_s32() #0 { ret void }
define void @test_fptosi_s64() #0 { ret void }
define void @test_fptoui_s32() #0 { ret void }
define void @test_fptoui_s64() #0 { ret void }
define void @test_sitofp_s32() #0 { ret void }
define void @test_sitofp_s64() #0 { ret void }
define void @test_uitofp_s32() #0 { ret void }
define void @test_uitofp_s64() #0 { ret void }
define void @test_add_no_fold_imm_s32() #2 { ret void }
define void @test_sub_s32() { ret void }
define void @test_sub_imm_s32() { ret void }
define void @test_sub_rev_imm_s32() { ret void }
define void @test_mul_s32() #1 { ret void }
define void @test_mul_s32() #0 { ret void }
define void @test_mulv5_s32() { ret void }
define void @test_sdiv_s32() #2 { ret void }
define void @test_udiv_s32() #2 { ret void }
define void @test_sdiv_s32() #1 { ret void }
define void @test_udiv_s32() #1 { ret void }
define void @test_lshr_s32() { ret void }
define void @test_ashr_s32() { ret void }
define void @test_shl_s32() { ret void }
define void @test_load_from_stack() { ret void }
define void @test_load_f32() #0 { ret void }
define void @test_load_f64() #0 { ret void }
define void @test_stores() #0 { ret void }
define void @test_stores() { ret void }
define void @test_gep() { ret void }
define void @test_MOVi32imm() #3 { ret void }
define void @test_MOVi32imm() #2 { ret void }
define void @test_constant_imm() { ret void }
define void @test_constant_cimm() { ret void }
@ -82,15 +48,10 @@
define void @test_br() { ret void }
define void @test_phi_s32() { ret void }
define void @test_phi_s64() #0 { ret void }
define void @test_soft_fp_double() #0 { ret void }
attributes #0 = { "target-features"="+vfp2,-neonfp" }
attributes #1 = { "target-features"="+v6" }
attributes #2 = { "target-features"="+hwdiv-arm" }
attributes #3 = { "target-features"="+v6t2" }
attributes #4 = { "target-features"="+vfp4,-neonfp" }
attributes #0 = { "target-features"="+v6" }
attributes #1 = { "target-features"="+hwdiv-arm" }
attributes #2 = { "target-features"="+v6t2" }
...
---
name: test_trunc_and_zext_s1
@ -268,36 +229,6 @@ body: |
; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_s64
# CHECK-LABEL: name: test_trunc_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0, $d0
%0(s64) = COPY $d0
; CHECK: [[VREG:%[0-9]+]]:dpr = COPY $d0
%2(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_TRUNC %0(s64)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]]
G_STORE %1(s32), %2 :: (store 4)
; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14, $noreg
BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
...
---
name: test_add_s32
# CHECK-LABEL: name: test_add_s32
legalized: true
@ -386,635 +317,6 @@ body: |
; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fadd_s32
# CHECK-LABEL: name: test_fadd_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $s0, $s1
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %2(s32)
; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fadd_s64
# CHECK-LABEL: name: test_fadd_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0, $d1
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fsub_s32
# CHECK-LABEL: name: test_fsub_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $s0, $s1
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FSUB %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %2(s32)
; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fsub_s64
# CHECK-LABEL: name: test_fsub_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0, $d1
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FSUB %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fmul_s32
# CHECK-LABEL: name: test_fmul_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $s0, $s1
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FMUL %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %2(s32)
; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fmul_s64
# CHECK-LABEL: name: test_fmul_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0, $d1
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FMUL %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fdiv_s32
# CHECK-LABEL: name: test_fdiv_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $s0, $s1
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FDIV %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %2(s32)
; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fdiv_s64
# CHECK-LABEL: name: test_fdiv_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0, $d1
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FDIV %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fneg_s32
# CHECK-LABEL: name: test_fneg_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $s0
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FNEG %0
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14, $noreg
$s0 = COPY %1(s32)
; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fneg_s64
# CHECK-LABEL: name: test_fneg_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = G_FNEG %0
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14, $noreg
$d0 = COPY %1(s64)
; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fma_s32
# CHECK-LABEL: name: test_fma_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
- { id: 3, class: fprb }
body: |
bb.0:
liveins: $s0, $s1, $s2
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = COPY $s2
; CHECK: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FMA %0, %1, %2
; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %3(s32)
; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fma_s64
# CHECK-LABEL: name: test_fma_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
- { id: 3, class: fprb }
body: |
bb.0:
liveins: $d0, $d1, $d2
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = COPY $d2
; CHECK: [[VREGZ:%[0-9]+]]:dpr = COPY $d2
%3(s64) = G_FMA %0, %1, %2
; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %3(s64)
; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fpext_s32_to_s64
# CHECK-LABEL: name: test_fpext_s32_to_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $s0
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s64) = G_FPEXT %0(s32)
; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14, $noreg
$d0 = COPY %1(s64)
; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fptrunc_s64_to_s32
# CHECK-LABEL: name: test_fptrunc_s64_to_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $d0
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTRUNC %0(s64)
; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14, $noreg
$s0 = COPY %1(s32)
; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fptosi_s32
# CHECK-LABEL: name: test_fptosi_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: $s0
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FPTOSI %0(s32)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
$r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptosi_s64
# CHECK-LABEL: name: test_fptosi_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: $d0
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTOSI %0(s64)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
$r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_s32
# CHECK-LABEL: name: test_fptoui_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: $s0
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FPTOUI %0(s32)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
$r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_s64
# CHECK-LABEL: name: test_fptoui_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: $d0
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTOUI %0(s64)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
$r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_sitofp_s32
# CHECK-LABEL: name: test_sitofp_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
%0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_SITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14, $noreg
$s0 = COPY %1(s32)
; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_sitofp_s64
# CHECK-LABEL: name: test_sitofp_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
%0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s64) = G_SITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14, $noreg
$d0 = COPY %1(s64)
; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_uitofp_s32
# CHECK-LABEL: name: test_uitofp_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
%0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_UITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14, $noreg
$s0 = COPY %1(s32)
; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_uitofp_s64
# CHECK-LABEL: name: test_uitofp_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
%0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s64) = G_UITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14, $noreg
$d0 = COPY %1(s64)
; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_sub_s32
# CHECK-LABEL: name: test_sub_s32
legalized: true
@ -1358,58 +660,6 @@ body: |
; CHECK: BX_RET 14, $noreg
...
---
name: test_load_f32
# CHECK-LABEL: name: test_load_f32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
%0(p0) = COPY $r0
; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s32) = G_LOAD %0(p0) :: (load 4)
; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, $noreg
$s0 = COPY %1
; CHECK: $s0 = COPY %[[V]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_load_f64
# CHECK-LABEL: name: test_load_f64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
%0(p0) = COPY $r0
; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s64) = G_LOAD %0(p0) :: (load 8)
; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, $noreg
$d0 = COPY %1
; CHECK: $d0 = COPY %[[V]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_stores
# CHECK-LABEL: name: test_stores
legalized: true
@ -1421,22 +671,16 @@ registers:
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: fprb }
- { id: 5, class: fprb }
# CHECK: id: [[P:[0-9]+]], class: gpr
# CHECK: id: [[I8:[0-9]+]], class: gpr
# CHECK: id: [[I16:[0-9]+]], class: gpr
# CHECK: id: [[I32:[0-9]+]], class: gpr
# CHECK: id: [[F32:[0-9]+]], class: spr
# CHECK: id: [[F64:[0-9]+]], class: dpr
body: |
bb.0:
liveins: $r0, $r1, $s0, $d0
liveins: $r0, $r1
%0(p0) = COPY $r0
%3(s32) = COPY $r1
%4(s32) = COPY $s0
%5(s64) = COPY $d2
%1(s8) = G_TRUNC %3(s32)
%2(s16) = G_TRUNC %3(s32)
@ -1449,12 +693,6 @@ body: |
G_STORE %3(s32), %0(p0) :: (store 4)
; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, $noreg
G_STORE %4(s32), %0(p0) :: (store 4)
; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, $noreg
G_STORE %5(s64), %0(p0) :: (store 8)
; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, $noreg
BX_RET 14, $noreg
...
---
@ -1775,87 +1013,3 @@ body: |
$r0 = COPY %4(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_phi_s64
# CHECK-LABEL: name: test_phi_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: fprb }
- { id: 3, class: fprb }
- { id: 4, class: fprb }
body: |
bb.0:
; CHECK: [[BB1:bb.0]]:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $d0, $d1
%0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
%2(s64) = COPY $d0
%3(s64) = COPY $d1
; CHECK: [[V1:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[V2:%[0-9]+]]:dpr = COPY $d1
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
bb.1:
; CHECK: [[BB2:bb.1]]:
successors: %bb.2(0x80000000)
G_BR %bb.2
; CHECK: B %bb.2
bb.2:
; CHECK: bb.2
%4(s64) = G_PHI %2(s64), %bb.0, %3(s64), %bb.1
; CHECK: {{%[0-9]+}}:dpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]]
$d0 = COPY %4(s64)
BX_RET 14, $noreg, implicit $d0
...
---
name: test_soft_fp_double
# CHECK-LABEL: name: test_soft_fp_double
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: fprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
%0(s32) = COPY $r2
; CHECK: [[IN1:%[0-9]+]]:gpr = COPY $r2
%1(s32) = COPY $r3
; CHECK: [[IN2:%[0-9]+]]:gpr = COPY $r3
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
; CHECK: %[[DREG:[0-9]+]]:dpr = VMOVDRR [[IN1]], [[IN2]]
%3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]]
$r0 = COPY %3
; CHECK: $r0 = COPY [[OUT1]]
$r1 = COPY %4
; CHECK: $r1 = COPY [[OUT2]]
BX_RET 14, $noreg, implicit $r0, implicit $r1
; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
...

227
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
View File

@ -1,6 +1,9 @@
# RUN: llc -O0 -mtriple arm-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD
# RUN: llc -O0 -mtriple arm-linux-gnueabi -mattr=+vfp2,+soft-float -float-abi=soft -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-AEABI
# RUN: llc -O0 -mtriple arm-linux-gnu -mattr=+soft-float -float-abi=soft -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-DEFAULT
# RUN: llc -O0 -mtriple thumb-linux-gnueabihf -mattr=+v6t2,+vfp2 -float-abi=hard -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD
# RUN: llc -O0 -mtriple thumb-linux-gnueabi -mattr=+v6t2,+vfp2,+soft-float -float-abi=soft -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-AEABI
# RUN: llc -O0 -mtriple thumb-linux-gnu -mattr=+v6t2,+soft-float -float-abi=soft -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-DEFAULT
--- |
define void @test_frem_float() { ret void }
define void @test_frem_double() { ret void }
@ -103,8 +106,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[Y]]
; HARD-DAG: $s0 = COPY [[X]]
; HARD-DAG: $s1 = COPY [[Y]]
; SOFT: BL &fmodf, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; HARD: BL &fmodf, {{.*}}, implicit $s0, implicit $s1, implicit-def $s0
; SOFT: BL{{.*}} &fmodf, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; HARD: BL{{.*}} &fmodf, {{.*}}, implicit $s0, implicit $s1, implicit-def $s0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP
@ -162,8 +165,8 @@ body: |
; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
; HARD-DAG: $d0 = COPY [[X]]
; HARD-DAG: $d1 = COPY [[Y]]
; SOFT: BL &fmod, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; HARD: BL &fmod, {{.*}}, implicit $d0, implicit $d1, implicit-def $d0
; SOFT: BL{{.*}} &fmod, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; HARD: BL{{.*}} &fmod, {{.*}}, implicit $d0, implicit $d1, implicit-def $d0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FREM
%6(s64) = G_FREM %4, %5
@ -198,8 +201,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[Y]]
; HARD-DAG: $s0 = COPY [[X]]
; HARD-DAG: $s1 = COPY [[Y]]
; SOFT: BL &powf, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; HARD: BL &powf, {{.*}}, implicit $s0, implicit $s1, implicit-def $s0
; SOFT: BL{{.*}} &powf, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; HARD: BL{{.*}} &powf, {{.*}}, implicit $s0, implicit $s1, implicit-def $s0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP
@ -257,8 +260,8 @@ body: |
; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
; HARD-DAG: $d0 = COPY [[X]]
; HARD-DAG: $d1 = COPY [[Y]]
; SOFT: BL &pow, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; HARD: BL &pow, {{.*}}, implicit $d0, implicit $d1, implicit-def $d0
; SOFT: BL{{.*}} &pow, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; HARD: BL{{.*}} &pow, {{.*}}, implicit $d0, implicit $d1, implicit-def $d0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FPOW
%6(s64) = G_FPOW %4, %5
@ -292,8 +295,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fadd, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__addsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fadd, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__addsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FADD
@ -343,8 +346,8 @@ body: |
; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dadd, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL &__adddf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-AEABI: BL{{.*}} &__aeabi_dadd, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__adddf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FADD
%6(s64) = G_FADD %4, %5
@ -379,8 +382,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fsub, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__subsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fsub, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__subsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FSUB
@ -430,8 +433,8 @@ body: |
; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dsub, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL &__subdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-AEABI: BL{{.*}} &__aeabi_dsub, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__subdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FSUB
%6(s64) = G_FSUB %4, %5
@ -466,8 +469,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fmul, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__mulsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fmul, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__mulsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMUL
@ -517,8 +520,8 @@ body: |
; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dmul, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL &__muldf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-AEABI: BL{{.*}} &__aeabi_dmul, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__muldf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMUL
%6(s64) = G_FMUL %4, %5
@ -553,8 +556,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fdiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__divsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fdiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__divsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FDIV
@ -604,8 +607,8 @@ body: |
; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_ddiv, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL &__divdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-AEABI: BL{{.*}} &__aeabi_ddiv, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__divdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FDIV
%6(s64) = G_FDIV %4, %5
@ -691,8 +694,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[ZERO]]
; SOFT-DAG: $r1 = COPY [[X]]
; SOFT-AEABI: BL &__aeabi_fsub, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__subsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fsub, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__subsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FNEG
@ -735,8 +738,8 @@ body: |
; SOFT-DAG: $r{{[0-1]}} = COPY [[POSITIVE_ZERO]]
; SOFT-DAG: $r{{[2-3]}} = COPY [[X0]]
; SOFT-DAG: $r{{[2-3]}} = COPY [[X1]]
; SOFT-AEABI: BL &__aeabi_dsub, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL &__subdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-AEABI: BL{{.*}} &__aeabi_dsub, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__subdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FNEG
%3(s64) = G_FNEG %2
@ -769,8 +772,8 @@ body: |
; SOFT-NOT: G_FPEXT
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-AEABI: BL &__aeabi_f2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL &__extendsfdf2, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-AEABI: BL{{.*}} &__aeabi_f2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__extendsfdf2, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; SOFT: ADJCALLSTACKUP
@ -812,8 +815,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X0]]
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-AEABI: BL &__aeabi_d2f, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__truncdfsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_d2f, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__truncdfsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTRUNC
@ -843,8 +846,8 @@ body: |
; SOFT-NOT: G_FPTOSI
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-AEABI: BL &__aeabi_f2iz, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-DEFAULT: BL &__fixsfsi, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_f2iz, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__fixsfsi, {{.*}}, implicit $r0, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOSI
@ -881,8 +884,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
; SOFT-AEABI: BL &__aeabi_d2iz, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__fixdfsi, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_d2iz, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__fixdfsi, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOSI
@ -912,8 +915,8 @@ body: |
; SOFT-NOT: G_FPTOUI
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-AEABI: BL &__aeabi_f2uiz, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-DEFAULT: BL &__fixunssfsi, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_f2uiz, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__fixunssfsi, {{.*}}, implicit $r0, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOUI
@ -950,8 +953,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
; SOFT-AEABI: BL &__aeabi_d2uiz, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__fixunsdfsi, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_d2uiz, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__fixunsdfsi, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOUI
@ -981,8 +984,8 @@ body: |
; SOFT-NOT: G_SITOFP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-AEABI: BL &__aeabi_i2f, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-DEFAULT: BL &__floatsisf, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_i2f, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__floatsisf, {{.*}}, implicit $r0, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SITOFP
@ -1014,8 +1017,8 @@ body: |
; SOFT-NOT: G_SITOFP
; SOFT: ADJCALLSTACKDOWN
; SOFT: $r0 = COPY [[X]]
; SOFT-AEABI: BL &__aeabi_i2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL &__floatsidf, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-AEABI: BL{{.*}} &__aeabi_i2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__floatsidf, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; SOFT-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; SOFT: ADJCALLSTACKUP
@ -1050,8 +1053,8 @@ body: |
; SOFT-NOT: G_UITOFP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-AEABI: BL &__aeabi_ui2f, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-DEFAULT: BL &__floatunsisf, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_ui2f, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__floatunsisf, {{.*}}, implicit $r0, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UITOFP
@ -1083,8 +1086,8 @@ body: |
; SOFT-NOT: G_UITOFP
; SOFT: ADJCALLSTACKDOWN
; SOFT: $r0 = COPY [[X]]
; SOFT-AEABI: BL &__aeabi_ui2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL &__floatunsidf, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-AEABI: BL{{.*}} &__aeabi_ui2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__floatunsidf, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; SOFT-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; SOFT: ADJCALLSTACKUP
@ -1200,8 +1203,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__eqsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__eqsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
@ -1246,8 +1249,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
@ -1292,8 +1295,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmpge, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__gesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpge, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
@ -1338,8 +1341,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
@ -1384,8 +1387,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmple, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__lesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmple, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__lesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
@ -1429,8 +1432,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -1469,8 +1472,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmple, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__lesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmple, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__lesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -1510,8 +1513,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -1551,8 +1554,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmpge, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__gesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpge, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -1592,8 +1595,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -1633,8 +1636,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__nesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__nesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -1675,8 +1678,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
@ -1721,8 +1724,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -1731,8 +1734,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -1781,8 +1784,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__eqsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__eqsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -1791,8 +1794,8 @@ body: |
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -1954,8 +1957,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__eqdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__eqdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
@ -2014,8 +2017,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
@ -2074,8 +2077,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmpge, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__gedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpge, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
@ -2134,8 +2137,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
@ -2194,8 +2197,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmple, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__ledf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmple, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ledf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
@ -2253,8 +2256,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -2307,8 +2310,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmple, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__ledf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmple, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ledf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -2362,8 +2365,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -2417,8 +2420,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmpge, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__gedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpge, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -2472,8 +2475,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -2527,8 +2530,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__nedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__nedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -2583,8 +2586,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
@ -2643,8 +2646,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -2655,8 +2658,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -2719,8 +2722,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__eqdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__eqdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -2731,8 +2734,8 @@ body: |
; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

871
llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir Normal file
View File

@ -0,0 +1,871 @@
# RUN: llc -O0 -mtriple arm-- -mattr=+vfp4,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp4,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
define void @test_trunc_s64() { ret void }
define void @test_fadd_s32() { ret void }
define void @test_fadd_s64() { ret void }
define void @test_fsub_s32() { ret void }
define void @test_fsub_s64() { ret void }
define void @test_fmul_s32() { ret void }
define void @test_fmul_s64() { ret void }
define void @test_fdiv_s32() { ret void }
define void @test_fdiv_s64() { ret void }
define void @test_fneg_s32() { ret void }
define void @test_fneg_s64() { ret void }
define void @test_fma_s32() { ret void }
define void @test_fma_s64() { ret void }
define void @test_fpext_s32_to_s64() { ret void }
define void @test_fptrunc_s64_to_s32() {ret void }
define void @test_fptosi_s32() { ret void }
define void @test_fptosi_s64() { ret void }
define void @test_fptoui_s32() { ret void }
define void @test_fptoui_s64() { ret void }
define void @test_sitofp_s32() { ret void }
define void @test_sitofp_s64() { ret void }
define void @test_uitofp_s32() { ret void }
define void @test_uitofp_s64() { ret void }
define void @test_load_f32() { ret void }
define void @test_load_f64() { ret void }
define void @test_stores() { ret void }
define void @test_phi_s64() { ret void }
define void @test_soft_fp_double() { ret void }
...
---
name: test_trunc_s64
# CHECK-LABEL: name: test_trunc_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0, $d0
%0(s64) = COPY $d0
; CHECK: [[VREG:%[0-9]+]]:dpr = COPY $d0
%2(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_TRUNC %0(s64)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]]
G_STORE %1(s32), %2 :: (store 4)
; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14, $noreg
BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
...
---
name: test_fadd_s32
# CHECK-LABEL: name: test_fadd_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $s0, $s1
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %2(s32)
; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fadd_s64
# CHECK-LABEL: name: test_fadd_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0, $d1
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fsub_s32
# CHECK-LABEL: name: test_fsub_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $s0, $s1
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FSUB %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %2(s32)
; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fsub_s64
# CHECK-LABEL: name: test_fsub_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0, $d1
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FSUB %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fmul_s32
# CHECK-LABEL: name: test_fmul_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $s0, $s1
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FMUL %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %2(s32)
; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fmul_s64
# CHECK-LABEL: name: test_fmul_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0, $d1
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FMUL %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fdiv_s32
# CHECK-LABEL: name: test_fdiv_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $s0, $s1
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FDIV %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %2(s32)
; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fdiv_s64
# CHECK-LABEL: name: test_fdiv_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0, $d1
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FDIV %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fneg_s32
# CHECK-LABEL: name: test_fneg_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $s0
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FNEG %0
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14, $noreg
$s0 = COPY %1(s32)
; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fneg_s64
# CHECK-LABEL: name: test_fneg_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = G_FNEG %0
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14, $noreg
$d0 = COPY %1(s64)
; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fma_s32
# CHECK-LABEL: name: test_fma_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
- { id: 3, class: fprb }
body: |
bb.0:
liveins: $s0, $s1, $s2
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = COPY $s2
; CHECK: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FMA %0, %1, %2
; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %3(s32)
; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fma_s64
# CHECK-LABEL: name: test_fma_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
- { id: 3, class: fprb }
body: |
bb.0:
liveins: $d0, $d1, $d2
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = COPY $d2
; CHECK: [[VREGZ:%[0-9]+]]:dpr = COPY $d2
%3(s64) = G_FMA %0, %1, %2
; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %3(s64)
; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fpext_s32_to_s64
# CHECK-LABEL: name: test_fpext_s32_to_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $s0
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s64) = G_FPEXT %0(s32)
; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14, $noreg
$d0 = COPY %1(s64)
; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fptrunc_s64_to_s32
# CHECK-LABEL: name: test_fptrunc_s64_to_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $d0
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTRUNC %0(s64)
; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14, $noreg
$s0 = COPY %1(s32)
; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fptosi_s32
# CHECK-LABEL: name: test_fptosi_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: $s0
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FPTOSI %0(s32)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
$r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptosi_s64
# CHECK-LABEL: name: test_fptosi_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: $d0
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTOSI %0(s64)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
$r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_s32
# CHECK-LABEL: name: test_fptoui_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: $s0
%0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FPTOUI %0(s32)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
$r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_s64
# CHECK-LABEL: name: test_fptoui_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: $d0
%0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTOUI %0(s64)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
$r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_sitofp_s32
# CHECK-LABEL: name: test_sitofp_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
%0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_SITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14, $noreg
$s0 = COPY %1(s32)
; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_sitofp_s64
# CHECK-LABEL: name: test_sitofp_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
%0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s64) = G_SITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14, $noreg
$d0 = COPY %1(s64)
; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_uitofp_s32
# CHECK-LABEL: name: test_uitofp_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
%0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_UITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14, $noreg
$s0 = COPY %1(s32)
; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_uitofp_s64
# CHECK-LABEL: name: test_uitofp_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
%0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s64) = G_UITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14, $noreg
$d0 = COPY %1(s64)
; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_load_f32
# CHECK-LABEL: name: test_load_f32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
%0(p0) = COPY $r0
; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s32) = G_LOAD %0(p0) :: (load 4)
; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, $noreg
$s0 = COPY %1
; CHECK: $s0 = COPY %[[V]]
BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_load_f64
# CHECK-LABEL: name: test_load_f64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
%0(p0) = COPY $r0
; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s64) = G_LOAD %0(p0) :: (load 8)
; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, $noreg
$d0 = COPY %1
; CHECK: $d0 = COPY %[[V]]
BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_stores
# CHECK-LABEL: name: test_stores
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
# CHECK: id: [[P:[0-9]+]], class: gpr
# CHECK: id: [[F32:[0-9]+]], class: spr
# CHECK: id: [[F64:[0-9]+]], class: dpr
body: |
bb.0:
liveins: $r0, $s0, $d0
%0(p0) = COPY $r0
%1(s32) = COPY $s0
%2(s64) = COPY $d2
G_STORE %1(s32), %0(p0) :: (store 4)
; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, $noreg
G_STORE %2(s64), %0(p0) :: (store 8)
; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, $noreg
BX_RET 14, $noreg
...
---
name: test_phi_s64
# CHECK-LABEL: name: test_phi_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: fprb }
- { id: 3, class: fprb }
- { id: 4, class: fprb }
body: |
bb.0:
; CHECK: [[BB1:bb.0]]:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $d0, $d1
%0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
%2(s64) = COPY $d0
%3(s64) = COPY $d1
; CHECK: [[V1:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[V2:%[0-9]+]]:dpr = COPY $d1
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
bb.1:
; CHECK: [[BB2:bb.1]]:
successors: %bb.2(0x80000000)
G_BR %bb.2
; CHECK: B %bb.2
bb.2:
; CHECK: bb.2
%4(s64) = G_PHI %2(s64), %bb.0, %3(s64), %bb.1
; CHECK: {{%[0-9]+}}:dpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]]
$d0 = COPY %4(s64)
BX_RET 14, $noreg, implicit $d0
...
---
name: test_soft_fp_double
# CHECK-LABEL: name: test_soft_fp_double
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: fprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
%0(s32) = COPY $r2
; CHECK: [[IN1:%[0-9]+]]:gpr = COPY $r2
%1(s32) = COPY $r3
; CHECK: [[IN2:%[0-9]+]]:gpr = COPY $r3
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
; CHECK: %[[DREG:[0-9]+]]:dpr = VMOVDRR [[IN1]], [[IN2]]
%3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]]
$r0 = COPY %3
; CHECK: $r0 = COPY [[OUT1]]
$r1 = COPY %4
; CHECK: $r1 = COPY [[OUT2]]
BX_RET 14, $noreg, implicit $r0, implicit $r1
; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
...