forked from OSchip/llvm-project
[X86] Use for loops over types to reduce code for setting up operation actions.
llvm-svn: 265893
This commit is contained in:
parent
dcc8f49bf0
commit
35db8ecb50
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@ -296,22 +296,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::BR_JT , MVT::Other, Expand);
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setOperationAction(ISD::BRCOND , MVT::Other, Custom);
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setOperationAction(ISD::BR_CC , MVT::f32, Expand);
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setOperationAction(ISD::BR_CC , MVT::f64, Expand);
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setOperationAction(ISD::BR_CC , MVT::f80, Expand);
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setOperationAction(ISD::BR_CC , MVT::f128, Expand);
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setOperationAction(ISD::BR_CC , MVT::i8, Expand);
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setOperationAction(ISD::BR_CC , MVT::i16, Expand);
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setOperationAction(ISD::BR_CC , MVT::i32, Expand);
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setOperationAction(ISD::BR_CC , MVT::i64, Expand);
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setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
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setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
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setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
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setOperationAction(ISD::SELECT_CC , MVT::f128, Expand);
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setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
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setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
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setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
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setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
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for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
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MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
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setOperationAction(ISD::BR_CC, VT, Expand);
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setOperationAction(ISD::SELECT_CC, VT, Expand);
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}
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if (Subtarget.is64Bit())
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
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@ -414,27 +403,16 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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// These should be promoted to a larger select which is supported.
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setOperationAction(ISD::SELECT , MVT::i1 , Promote);
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// X86 wants to expand cmov itself.
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setOperationAction(ISD::SELECT , MVT::i8 , Custom);
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setOperationAction(ISD::SELECT , MVT::i16 , Custom);
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setOperationAction(ISD::SELECT , MVT::i32 , Custom);
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setOperationAction(ISD::SELECT , MVT::f32 , Custom);
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setOperationAction(ISD::SELECT , MVT::f64 , Custom);
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setOperationAction(ISD::SELECT , MVT::f80 , Custom);
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setOperationAction(ISD::SELECT , MVT::f128 , Custom);
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setOperationAction(ISD::SETCC , MVT::i8 , Custom);
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setOperationAction(ISD::SETCC , MVT::i16 , Custom);
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setOperationAction(ISD::SETCC , MVT::i32 , Custom);
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setOperationAction(ISD::SETCC , MVT::f32 , Custom);
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setOperationAction(ISD::SETCC , MVT::f64 , Custom);
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setOperationAction(ISD::SETCC , MVT::f80 , Custom);
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setOperationAction(ISD::SETCC , MVT::f128 , Custom);
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setOperationAction(ISD::SETCCE , MVT::i8 , Custom);
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setOperationAction(ISD::SETCCE , MVT::i16 , Custom);
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setOperationAction(ISD::SETCCE , MVT::i32 , Custom);
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if (Subtarget.is64Bit()) {
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setOperationAction(ISD::SELECT , MVT::i64 , Custom);
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setOperationAction(ISD::SETCC , MVT::i64 , Custom);
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setOperationAction(ISD::SETCCE , MVT::i64 , Custom);
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for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
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setOperationAction(ISD::SELECT, VT, Custom);
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setOperationAction(ISD::SETCC, VT, Custom);
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}
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for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
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if (VT == MVT::i64 && !Subtarget.is64Bit())
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continue;
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setOperationAction(ISD::SELECT, VT, Custom);
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::SETCCE, VT, Custom);
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}
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setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
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// NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
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@ -447,29 +425,23 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
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// Darwin ABI issue.
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setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
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setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
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setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
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if (Subtarget.is64Bit())
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setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
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setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
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setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
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if (Subtarget.is64Bit()) {
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setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
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setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
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setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
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setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
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setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
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for (auto VT : { MVT::i32, MVT::i64 }) {
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if (VT == MVT::i64 && !Subtarget.is64Bit())
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continue;
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setOperationAction(ISD::ConstantPool , VT, Custom);
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setOperationAction(ISD::JumpTable , VT, Custom);
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setOperationAction(ISD::GlobalAddress , VT, Custom);
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setOperationAction(ISD::GlobalTLSAddress, VT, Custom);
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setOperationAction(ISD::ExternalSymbol , VT, Custom);
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setOperationAction(ISD::BlockAddress , VT, Custom);
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}
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// 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
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setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
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setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
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setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
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if (Subtarget.is64Bit()) {
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setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
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setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
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setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
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for (auto VT : { MVT::i32, MVT::i64 }) {
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if (VT == MVT::i64 && !Subtarget.is64Bit())
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continue;
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setOperationAction(ISD::SHL_PARTS, VT, Custom);
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setOperationAction(ISD::SRA_PARTS, VT, Custom);
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setOperationAction(ISD::SRL_PARTS, VT, Custom);
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}
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if (Subtarget.hasSSE1())
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@ -534,30 +506,26 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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addRegisterClass(MVT::f32, &X86::FR32RegClass);
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addRegisterClass(MVT::f64, &X86::FR64RegClass);
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// Use ANDPD to simulate FABS.
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setOperationAction(ISD::FABS , MVT::f64, Custom);
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setOperationAction(ISD::FABS , MVT::f32, Custom);
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for (auto VT : { MVT::f32, MVT::f64 }) {
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// Use ANDPD to simulate FABS.
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setOperationAction(ISD::FABS, VT, Custom);
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// Use XORP to simulate FNEG.
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setOperationAction(ISD::FNEG , MVT::f64, Custom);
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setOperationAction(ISD::FNEG , MVT::f32, Custom);
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// Use XORP to simulate FNEG.
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setOperationAction(ISD::FNEG, VT, Custom);
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// Use ANDPD and ORPD to simulate FCOPYSIGN.
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
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// Use ANDPD and ORPD to simulate FCOPYSIGN.
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setOperationAction(ISD::FCOPYSIGN, VT, Custom);
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// We don't support sin/cos/fmod
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setOperationAction(ISD::FSIN , VT, Expand);
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setOperationAction(ISD::FCOS , VT, Expand);
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setOperationAction(ISD::FSINCOS, VT, Expand);
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}
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// Lower this to FGETSIGNx86 plus an AND.
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setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
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setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
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// We don't support sin/cos/fmod
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
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// Expand FP immediates into loads from the stack, except for the special
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// cases we handle.
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addLegalFPImmediate(APFloat(+0.0)); // xorpd
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@ -603,18 +571,15 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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addRegisterClass(MVT::f64, &X86::RFP64RegClass);
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addRegisterClass(MVT::f32, &X86::RFP32RegClass);
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setOperationAction(ISD::UNDEF, MVT::f64, Expand);
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setOperationAction(ISD::UNDEF, MVT::f32, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
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for (auto VT : { MVT::f32, MVT::f64 }) {
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setOperationAction(ISD::UNDEF, VT, Expand);
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setOperationAction(ISD::FCOPYSIGN, VT, Expand);
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if (!TM.Options.UnsafeFPMath) {
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
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if (!TM.Options.UnsafeFPMath) {
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setOperationAction(ISD::FSIN , VT, Expand);
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setOperationAction(ISD::FCOS , VT, Expand);
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setOperationAction(ISD::FSINCOS, VT, Expand);
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}
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}
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addLegalFPImmediate(APFloat(+0.0)); // FLD0
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addLegalFPImmediate(APFloat(+1.0)); // FLD1
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@ -906,18 +871,16 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
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}
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
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setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
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setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
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for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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setOperationAction(ISD::VSELECT, VT, Custom);
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if (Subtarget.is64Bit()) {
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
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if (VT == MVT::v2i64 && !Subtarget.is64Bit())
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continue;
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
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}
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// Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
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@ -1038,25 +1001,19 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
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setOperationAction(ISD::SRL, MVT::v8i16, Custom);
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setOperationAction(ISD::SRL, MVT::v16i8, Custom);
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setOperationAction(ISD::SHL, MVT::v8i16, Custom);
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setOperationAction(ISD::SHL, MVT::v16i8, Custom);
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setOperationAction(ISD::SRA, MVT::v8i16, Custom);
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setOperationAction(ISD::SRA, MVT::v16i8, Custom);
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for (auto VT : { MVT::v8i16, MVT::v16i8 }) {
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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}
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// In the customized shift lowering, the legal cases in AVX2 will be
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// recognized.
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setOperationAction(ISD::SRL, MVT::v2i64, Custom);
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setOperationAction(ISD::SRL, MVT::v4i32, Custom);
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setOperationAction(ISD::SHL, MVT::v2i64, Custom);
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setOperationAction(ISD::SHL, MVT::v4i32, Custom);
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setOperationAction(ISD::SRA, MVT::v2i64, Custom);
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setOperationAction(ISD::SRA, MVT::v4i32, Custom);
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for (auto VT : { MVT::v4i32, MVT::v2i64 }) {
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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}
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}
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if (Subtarget.hasXOP()) {
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@ -1484,21 +1441,14 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::MUL, MVT::v16i32, Legal);
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setOperationAction(ISD::SRL, MVT::v8i64, Custom);
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setOperationAction(ISD::SRL, MVT::v16i32, Custom);
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setOperationAction(ISD::SHL, MVT::v8i64, Custom);
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setOperationAction(ISD::SHL, MVT::v16i32, Custom);
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setOperationAction(ISD::SRA, MVT::v8i64, Custom);
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setOperationAction(ISD::SRA, MVT::v16i32, Custom);
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setOperationAction(ISD::AND, MVT::v8i64, Legal);
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setOperationAction(ISD::OR, MVT::v8i64, Legal);
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setOperationAction(ISD::XOR, MVT::v8i64, Legal);
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setOperationAction(ISD::AND, MVT::v16i32, Legal);
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setOperationAction(ISD::OR, MVT::v16i32, Legal);
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setOperationAction(ISD::XOR, MVT::v16i32, Legal);
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for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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setOperationAction(ISD::AND, VT, Legal);
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setOperationAction(ISD::OR, VT, Legal);
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setOperationAction(ISD::XOR, VT, Legal);
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}
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if (Subtarget.hasCDI()) {
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setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
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@ -1661,13 +1611,13 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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}
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for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::VSELECT, VT, Legal);
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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setOperationAction(ISD::MLOAD, VT, Legal);
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setOperationAction(ISD::MSTORE, VT, Legal);
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::VSELECT, VT, Legal);
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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setOperationAction(ISD::MLOAD, VT, Legal);
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setOperationAction(ISD::MSTORE, VT, Legal);
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setOperationAction(ISD::AND, VT, Promote);
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AddPromotedToType (ISD::AND, VT, MVT::v8i64);
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@ -1699,21 +1649,18 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
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setOperationAction(ISD::AND, MVT::v8i32, Legal);
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setOperationAction(ISD::OR, MVT::v8i32, Legal);
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setOperationAction(ISD::XOR, MVT::v8i32, Legal);
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setOperationAction(ISD::AND, MVT::v4i32, Legal);
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setOperationAction(ISD::OR, MVT::v4i32, Legal);
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setOperationAction(ISD::XOR, MVT::v4i32, Legal);
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for (auto VT : { MVT::v4i32, MVT::v8i32 }) {
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setOperationAction(ISD::AND, VT, Legal);
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setOperationAction(ISD::OR, VT, Legal);
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setOperationAction(ISD::XOR, VT, Legal);
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}
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setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
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setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
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setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
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setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
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setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
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setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
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setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
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setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
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for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
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setOperationAction(ISD::SMAX, VT, Legal);
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setOperationAction(ISD::UMAX, VT, Legal);
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setOperationAction(ISD::SMIN, VT, Legal);
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setOperationAction(ISD::UMIN, VT, Legal);
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}
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}
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// We want to custom lower some of our intrinsics.
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