forked from OSchip/llvm-project
[X86] Remove remaining gpr schedule itineraries (PR37093)
llvm-svn: 329938
This commit is contained in:
Simon Pilgrim
parent
e708a09e21
commit
35935c0632
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@ -18,24 +18,24 @@ let SchedRW = [WriteLEA] in {
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let hasSideEffects = 0 in
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def LEA16r : I<0x8D, MRMSrcMem,
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(outs GR16:$dst), (ins anymem:$src),
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"lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize16;
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"lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize16;
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let isReMaterializable = 1 in
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def LEA32r : I<0x8D, MRMSrcMem,
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(outs GR32:$dst), (ins anymem:$src),
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"lea{l}\t{$src|$dst}, {$dst|$src}",
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[(set GR32:$dst, lea32addr:$src)], IIC_LEA>,
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[(set GR32:$dst, lea32addr:$src)]>,
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OpSize32, Requires<[Not64BitMode]>;
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def LEA64_32r : I<0x8D, MRMSrcMem,
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(outs GR32:$dst), (ins lea64_32mem:$src),
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"lea{l}\t{$src|$dst}, {$dst|$src}",
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[(set GR32:$dst, lea64_32addr:$src)], IIC_LEA>,
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[(set GR32:$dst, lea64_32addr:$src)]>,
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OpSize32, Requires<[In64BitMode]>;
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let isReMaterializable = 1 in
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def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
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"lea{q}\t{$src|$dst}, {$dst|$src}",
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[(set GR64:$dst, lea64addr:$src)], IIC_LEA>;
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[(set GR64:$dst, lea64addr:$src)]>;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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@ -63,24 +63,24 @@ def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
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// This probably ought to be moved to a def : Pat<> if the
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// syntax can be accepted.
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[(set AL, (mul AL, GR8:$src)),
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(implicit EFLAGS)], IIC_MUL8_REG>, Sched<[WriteIMul]>;
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(implicit EFLAGS)]>, Sched<[WriteIMul]>;
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// AX,DX = AX*GR16
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let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
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def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
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"mul{w}\t$src",
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[], IIC_MUL16_REG>, OpSize16, Sched<[WriteIMul]>;
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[]>, OpSize16, Sched<[WriteIMul]>;
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// EAX,EDX = EAX*GR32
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in
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def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
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"mul{l}\t$src",
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[/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/],
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IIC_MUL32_REG>, OpSize32, Sched<[WriteIMul]>;
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[/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/]>,
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OpSize32, Sched<[WriteIMul]>;
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// RAX,RDX = RAX*GR64
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
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def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
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"mul{q}\t$src",
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[/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
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IIC_MUL64_REG>, Sched<[WriteIMul]>;
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[/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/]>,
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Sched<[WriteIMul]>;
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// AL,AH = AL*[mem8]
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let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
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@ -89,62 +89,58 @@ def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
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// This probably ought to be moved to a def : Pat<> if the
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// syntax can be accepted.
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[(set AL, (mul AL, (loadi8 addr:$src))),
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(implicit EFLAGS)], IIC_MUL8_MEM>, SchedLoadReg<WriteIMulLd>;
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(implicit EFLAGS)]>, SchedLoadReg<WriteIMulLd>;
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// AX,DX = AX*[mem16]
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let mayLoad = 1, hasSideEffects = 0 in {
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let Defs = [AX,DX,EFLAGS], Uses = [AX] in
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def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
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"mul{w}\t$src",
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[], IIC_MUL16_MEM>, OpSize16, SchedLoadReg<WriteIMulLd>;
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"mul{w}\t$src", []>, OpSize16, SchedLoadReg<WriteIMulLd>;
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// EAX,EDX = EAX*[mem32]
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
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"mul{l}\t$src",
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[], IIC_MUL32_MEM>, OpSize32, SchedLoadReg<WriteIMulLd>;
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"mul{l}\t$src", []>, OpSize32, SchedLoadReg<WriteIMulLd>;
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// RAX,RDX = RAX*[mem64]
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
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"mul{q}\t$src", [], IIC_MUL64_MEM>, SchedLoadReg<WriteIMulLd>,
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"mul{q}\t$src", []>, SchedLoadReg<WriteIMulLd>,
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Requires<[In64BitMode]>;
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}
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let hasSideEffects = 0 in {
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// AL,AH = AL*GR8
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let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", [],
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IIC_IMUL8_REG>, Sched<[WriteIMul]>;
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def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>,
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Sched<[WriteIMul]>;
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// AX,DX = AX*GR16
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let Defs = [AX,DX,EFLAGS], Uses = [AX] in
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def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [],
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IIC_IMUL16_REG>, OpSize16, Sched<[WriteIMul]>;
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def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
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OpSize16, Sched<[WriteIMul]>;
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// EAX,EDX = EAX*GR32
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [],
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IIC_IMUL32_REG>, OpSize32, Sched<[WriteIMul]>;
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def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>,
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OpSize32, Sched<[WriteIMul]>;
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// RAX,RDX = RAX*GR64
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [],
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IIC_IMUL64_REG>, Sched<[WriteIMul]>;
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def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>,
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Sched<[WriteIMul]>;
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let mayLoad = 1 in {
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// AL,AH = AL*[mem8]
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let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
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"imul{b}\t$src", [], IIC_IMUL8_MEM>, SchedLoadReg<WriteIMulLd>;
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"imul{b}\t$src", []>, SchedLoadReg<WriteIMulLd>;
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// AX,DX = AX*[mem16]
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let Defs = [AX,DX,EFLAGS], Uses = [AX] in
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def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
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"imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize16,
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SchedLoadReg<WriteIMulLd>;
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"imul{w}\t$src", []>, OpSize16, SchedLoadReg<WriteIMulLd>;
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// EAX,EDX = EAX*[mem32]
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
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"imul{l}\t$src", [], IIC_IMUL32_MEM>, OpSize32,
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SchedLoadReg<WriteIMulLd>;
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"imul{l}\t$src", []>, OpSize32, SchedLoadReg<WriteIMulLd>;
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// RAX,RDX = RAX*[mem64]
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
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"imul{q}\t$src", [], IIC_IMUL64_MEM>, SchedLoadReg<WriteIMulLd>,
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"imul{q}\t$src", []>, SchedLoadReg<WriteIMulLd>,
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Requires<[In64BitMode]>;
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}
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} // hasSideEffects
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@ -159,19 +155,16 @@ let isCommutable = 1, SchedRW = [WriteIMul] in {
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def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
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"imul{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag GR16:$src1, GR16:$src2))], IIC_IMUL16_RR>,
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TB, OpSize16;
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(X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize16;
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def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
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"imul{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, GR32:$src2))], IIC_IMUL32_RR>,
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TB, OpSize32;
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(X86smul_flag GR32:$src1, GR32:$src2))]>, TB, OpSize32;
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def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"imul{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag GR64:$src1, GR64:$src2))], IIC_IMUL64_RR>,
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TB;
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(X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
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} // isCommutable, SchedRW
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// Register-Memory Signed Integer Multiply
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@ -180,22 +173,19 @@ def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
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(ins GR16:$src1, i16mem:$src2),
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"imul{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag GR16:$src1, (loadi16 addr:$src2)))],
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IIC_IMUL16_RM>,
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(X86smul_flag GR16:$src1, (loadi16 addr:$src2)))]>,
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TB, OpSize16;
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def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
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(ins GR32:$src1, i32mem:$src2),
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"imul{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, (loadi32 addr:$src2)))],
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IIC_IMUL32_RM>,
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(X86smul_flag GR32:$src1, (loadi32 addr:$src2)))]>,
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TB, OpSize32;
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def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
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(ins GR64:$src1, i64mem:$src2),
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"imul{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag GR64:$src1, (loadi64 addr:$src2)))],
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IIC_IMUL64_RM>,
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(X86smul_flag GR64:$src1, (loadi64 addr:$src2)))]>,
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TB;
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} // SchedRW
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} // Constraints = "$src1 = $dst"
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@ -210,38 +200,36 @@ def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
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(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag GR16:$src1, imm:$src2))],
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IIC_IMUL16_RRI>, OpSize16;
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(X86smul_flag GR16:$src1, imm:$src2))]>,
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OpSize16;
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def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
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(outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
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"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag GR16:$src1, i16immSExt8:$src2))],
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IIC_IMUL16_RRI>, OpSize16;
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(X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
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OpSize16;
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def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
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(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, imm:$src2))],
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IIC_IMUL32_RRI>, OpSize32;
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(X86smul_flag GR32:$src1, imm:$src2))]>,
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OpSize32;
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def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
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(outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
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"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, i32immSExt8:$src2))],
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IIC_IMUL32_RRI>, OpSize32;
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(X86smul_flag GR32:$src1, i32immSExt8:$src2))]>,
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OpSize32;
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def IMUL64rri32 : RIi32S<0x69, MRMSrcReg, // GR64 = GR64*I32
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(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag GR64:$src1, i64immSExt32:$src2))],
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IIC_IMUL64_RRI>;
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(X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
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def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
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(outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag GR64:$src1, i64immSExt8:$src2))],
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IIC_IMUL64_RRI>;
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(X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
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} // SchedRW
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// Memory-Integer Signed Integer Multiply
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@ -250,43 +238,40 @@ def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
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(outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
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"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag (loadi16 addr:$src1), imm:$src2))],
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IIC_IMUL16_RMI>,
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OpSize16;
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(X86smul_flag (loadi16 addr:$src1), imm:$src2))]>,
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OpSize16;
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def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
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(outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
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"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag (loadi16 addr:$src1),
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i16immSExt8:$src2))], IIC_IMUL16_RMI>,
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OpSize16;
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i16immSExt8:$src2))]>,
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OpSize16;
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def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
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(outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
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"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag (loadi32 addr:$src1), imm:$src2))],
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IIC_IMUL32_RMI>, OpSize32;
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(X86smul_flag (loadi32 addr:$src1), imm:$src2))]>,
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OpSize32;
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def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
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(outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
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"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag (loadi32 addr:$src1),
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i32immSExt8:$src2))],
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IIC_IMUL32_RMI>, OpSize32;
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i32immSExt8:$src2))]>,
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OpSize32;
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def IMUL64rmi32 : RIi32S<0x69, MRMSrcMem, // GR64 = [mem64]*I32
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(outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag (loadi64 addr:$src1),
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i64immSExt32:$src2))],
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IIC_IMUL64_RMI>;
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i64immSExt32:$src2))]>;
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def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
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(outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag (loadi64 addr:$src1),
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i64immSExt8:$src2))],
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IIC_IMUL64_RMI>;
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i64immSExt8:$src2))]>;
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} // SchedRW
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} // Defs = [EFLAGS]
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@ -298,73 +283,68 @@ let hasSideEffects = 1 in { // so that we don't speculatively execute
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let SchedRW = [WriteIDiv] in {
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let Defs = [AL,AH,EFLAGS], Uses = [AX] in
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def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
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"div{b}\t$src", [], IIC_DIV8_REG>;
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||||
"div{b}\t$src", []>;
|
||||
let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
|
||||
def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
|
||||
"div{w}\t$src", [], IIC_DIV16_REG>, OpSize16;
|
||||
"div{w}\t$src", []>, OpSize16;
|
||||
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
|
||||
def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
|
||||
"div{l}\t$src", [], IIC_DIV32_REG>, OpSize32;
|
||||
"div{l}\t$src", []>, OpSize32;
|
||||
// RDX:RAX/r64 = RAX,RDX
|
||||
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
|
||||
def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
|
||||
"div{q}\t$src", [], IIC_DIV64_REG>;
|
||||
"div{q}\t$src", []>;
|
||||
} // SchedRW
|
||||
|
||||
let mayLoad = 1 in {
|
||||
let Defs = [AL,AH,EFLAGS], Uses = [AX] in
|
||||
def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
|
||||
"div{b}\t$src", [], IIC_DIV8_MEM>,
|
||||
SchedLoadReg<WriteIDivLd>;
|
||||
"div{b}\t$src", []>, SchedLoadReg<WriteIDivLd>;
|
||||
let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
|
||||
def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
|
||||
"div{w}\t$src", [], IIC_DIV16_MEM>, OpSize16,
|
||||
SchedLoadReg<WriteIDivLd>;
|
||||
"div{w}\t$src", []>, OpSize16, SchedLoadReg<WriteIDivLd>;
|
||||
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
|
||||
def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
|
||||
"div{l}\t$src", [], IIC_DIV32_MEM>,
|
||||
SchedLoadReg<WriteIDivLd>, OpSize32;
|
||||
"div{l}\t$src", []>, SchedLoadReg<WriteIDivLd>, OpSize32;
|
||||
// RDX:RAX/[mem64] = RAX,RDX
|
||||
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
|
||||
def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
|
||||
"div{q}\t$src", [], IIC_DIV64_MEM>,
|
||||
SchedLoadReg<WriteIDivLd>, Requires<[In64BitMode]>;
|
||||
"div{q}\t$src", []>, SchedLoadReg<WriteIDivLd>,
|
||||
Requires<[In64BitMode]>;
|
||||
}
|
||||
|
||||
// Signed division/remainder.
|
||||
let SchedRW = [WriteIDiv] in {
|
||||
let Defs = [AL,AH,EFLAGS], Uses = [AX] in
|
||||
def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
|
||||
"idiv{b}\t$src", [], IIC_IDIV8_REG>;
|
||||
"idiv{b}\t$src", []>;
|
||||
let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
|
||||
def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
|
||||
"idiv{w}\t$src", [], IIC_IDIV16_REG>, OpSize16;
|
||||
"idiv{w}\t$src", []>, OpSize16;
|
||||
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
|
||||
def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
|
||||
"idiv{l}\t$src", [], IIC_IDIV32_REG>, OpSize32;
|
||||
"idiv{l}\t$src", []>, OpSize32;
|
||||
// RDX:RAX/r64 = RAX,RDX
|
||||
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
|
||||
def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
|
||||
"idiv{q}\t$src", [], IIC_IDIV64_REG>;
|
||||
"idiv{q}\t$src", []>;
|
||||
} // SchedRW
|
||||
|
||||
let mayLoad = 1 in {
|
||||
let Defs = [AL,AH,EFLAGS], Uses = [AX] in
|
||||
def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
|
||||
"idiv{b}\t$src", [], IIC_IDIV8_MEM>,
|
||||
"idiv{b}\t$src", []>,
|
||||
SchedLoadReg<WriteIDivLd>;
|
||||
let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
|
||||
def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
|
||||
"idiv{w}\t$src", [], IIC_IDIV16_MEM>, OpSize16,
|
||||
SchedLoadReg<WriteIDivLd>;
|
||||
"idiv{w}\t$src", []>, OpSize16, SchedLoadReg<WriteIDivLd>;
|
||||
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
|
||||
def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
|
||||
"idiv{l}\t$src", [], IIC_IDIV32_MEM>, OpSize32,
|
||||
SchedLoadReg<WriteIDivLd>;
|
||||
"idiv{l}\t$src", []>, OpSize32, SchedLoadReg<WriteIDivLd>;
|
||||
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
|
||||
def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
|
||||
"idiv{q}\t$src", [], IIC_IDIV64_MEM>,
|
||||
SchedLoadReg<WriteIDivLd>, Requires<[In64BitMode]>;
|
||||
"idiv{q}\t$src", []>, SchedLoadReg<WriteIDivLd>,
|
||||
Requires<[In64BitMode]>;
|
||||
}
|
||||
} // hasSideEffects = 0
|
||||
|
||||
|
|
@ -379,18 +359,18 @@ let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
|
|||
def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
"neg{b}\t$dst",
|
||||
[(set GR8:$dst, (ineg GR8:$src1)),
|
||||
(implicit EFLAGS)], IIC_UNARY_REG>;
|
||||
(implicit EFLAGS)]>;
|
||||
def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"neg{w}\t$dst",
|
||||
[(set GR16:$dst, (ineg GR16:$src1)),
|
||||
(implicit EFLAGS)], IIC_UNARY_REG>, OpSize16;
|
||||
(implicit EFLAGS)]>, OpSize16;
|
||||
def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"neg{l}\t$dst",
|
||||
[(set GR32:$dst, (ineg GR32:$src1)),
|
||||
(implicit EFLAGS)], IIC_UNARY_REG>, OpSize32;
|
||||
(implicit EFLAGS)]>, OpSize32;
|
||||
def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
|
||||
[(set GR64:$dst, (ineg GR64:$src1)),
|
||||
(implicit EFLAGS)], IIC_UNARY_REG>;
|
||||
(implicit EFLAGS)]>;
|
||||
} // Constraints = "$src1 = $dst", SchedRW
|
||||
|
||||
// Read-modify-write negate.
|
||||
|
|
@ -398,18 +378,18 @@ let SchedRW = [WriteALURMW] in {
|
|||
def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
|
||||
"neg{b}\t$dst",
|
||||
[(store (ineg (loadi8 addr:$dst)), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
||||
(implicit EFLAGS)]>;
|
||||
def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
|
||||
"neg{w}\t$dst",
|
||||
[(store (ineg (loadi16 addr:$dst)), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize16;
|
||||
(implicit EFLAGS)]>, OpSize16;
|
||||
def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
|
||||
"neg{l}\t$dst",
|
||||
[(store (ineg (loadi32 addr:$dst)), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize32;
|
||||
(implicit EFLAGS)]>, OpSize32;
|
||||
def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
|
||||
[(store (ineg (loadi64 addr:$dst)), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
||||
(implicit EFLAGS)]>,
|
||||
Requires<[In64BitMode]>;
|
||||
} // SchedRW
|
||||
} // Defs = [EFLAGS]
|
||||
|
|
@ -422,32 +402,32 @@ let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
|
|||
let AddedComplexity = 15 in {
|
||||
def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
"not{b}\t$dst",
|
||||
[(set GR8:$dst, (not GR8:$src1))], IIC_UNARY_REG>;
|
||||
[(set GR8:$dst, (not GR8:$src1))]>;
|
||||
def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"not{w}\t$dst",
|
||||
[(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>, OpSize16;
|
||||
[(set GR16:$dst, (not GR16:$src1))]>, OpSize16;
|
||||
def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"not{l}\t$dst",
|
||||
[(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>, OpSize32;
|
||||
[(set GR32:$dst, (not GR32:$src1))]>, OpSize32;
|
||||
def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
|
||||
[(set GR64:$dst, (not GR64:$src1))], IIC_UNARY_REG>;
|
||||
[(set GR64:$dst, (not GR64:$src1))]>;
|
||||
}
|
||||
} // Constraints = "$src1 = $dst", SchedRW
|
||||
|
||||
let SchedRW = [WriteALURMW] in {
|
||||
def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
|
||||
"not{b}\t$dst",
|
||||
[(store (not (loadi8 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
|
||||
[(store (not (loadi8 addr:$dst)), addr:$dst)]>;
|
||||
def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
|
||||
"not{w}\t$dst",
|
||||
[(store (not (loadi16 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>,
|
||||
[(store (not (loadi16 addr:$dst)), addr:$dst)]>,
|
||||
OpSize16;
|
||||
def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
|
||||
"not{l}\t$dst",
|
||||
[(store (not (loadi32 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>,
|
||||
[(store (not (loadi32 addr:$dst)), addr:$dst)]>,
|
||||
OpSize32;
|
||||
def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
|
||||
[(store (not (loadi64 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>,
|
||||
[(store (not (loadi64 addr:$dst)), addr:$dst)]>,
|
||||
Requires<[In64BitMode]>;
|
||||
} // SchedRW
|
||||
} // CodeSize
|
||||
|
|
@ -458,29 +438,25 @@ let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
|
|||
let CodeSize = 2 in
|
||||
def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
"inc{b}\t$dst",
|
||||
[(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))],
|
||||
IIC_UNARY_REG>;
|
||||
[(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
|
||||
let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
|
||||
def INC16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"inc{w}\t$dst",
|
||||
[(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))],
|
||||
IIC_UNARY_REG>, OpSize16;
|
||||
[(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>, OpSize16;
|
||||
def INC32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"inc{l}\t$dst",
|
||||
[(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
|
||||
IIC_UNARY_REG>, OpSize32;
|
||||
[(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>, OpSize32;
|
||||
def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
|
||||
[(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))],
|
||||
IIC_UNARY_REG>;
|
||||
[(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))]>;
|
||||
} // isConvertibleToThreeAddress = 1, CodeSize = 2
|
||||
|
||||
// Short forms only valid in 32-bit mode. Selected during MCInst lowering.
|
||||
let CodeSize = 1, hasSideEffects = 0 in {
|
||||
def INC16r_alt : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"inc{w}\t$dst", [], IIC_UNARY_REG>,
|
||||
"inc{w}\t$dst", []>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def INC32r_alt : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"inc{l}\t$dst", [], IIC_UNARY_REG>,
|
||||
"inc{l}\t$dst", []>,
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
} // CodeSize = 1, hasSideEffects = 0
|
||||
} // Constraints = "$src1 = $dst", SchedRW
|
||||
|
|
@ -489,18 +465,18 @@ let CodeSize = 2, SchedRW = [WriteALURMW] in {
|
|||
let Predicates = [UseIncDec] in {
|
||||
def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
|
||||
[(store (add (loadi8 addr:$dst), 1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
||||
(implicit EFLAGS)]>;
|
||||
def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
|
||||
[(store (add (loadi16 addr:$dst), 1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize16;
|
||||
(implicit EFLAGS)]>, OpSize16;
|
||||
def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
|
||||
[(store (add (loadi32 addr:$dst), 1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize32;
|
||||
(implicit EFLAGS)]>, OpSize32;
|
||||
} // Predicates
|
||||
let Predicates = [UseIncDec, In64BitMode] in {
|
||||
def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
|
||||
[(store (add (loadi64 addr:$dst), 1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
||||
(implicit EFLAGS)]>;
|
||||
} // Predicates
|
||||
} // CodeSize = 2, SchedRW
|
||||
|
||||
|
|
@ -508,29 +484,25 @@ let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
|
|||
let CodeSize = 2 in
|
||||
def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
"dec{b}\t$dst",
|
||||
[(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))],
|
||||
IIC_UNARY_REG>;
|
||||
[(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
|
||||
let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
|
||||
def DEC16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"dec{w}\t$dst",
|
||||
[(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
|
||||
IIC_UNARY_REG>, OpSize16;
|
||||
[(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>, OpSize16;
|
||||
def DEC32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"dec{l}\t$dst",
|
||||
[(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
|
||||
IIC_UNARY_REG>, OpSize32;
|
||||
[(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>, OpSize32;
|
||||
def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
|
||||
[(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))],
|
||||
IIC_UNARY_REG>;
|
||||
[(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))]>;
|
||||
} // isConvertibleToThreeAddress = 1, CodeSize = 2
|
||||
|
||||
// Short forms only valid in 32-bit mode. Selected during MCInst lowering.
|
||||
let CodeSize = 1, hasSideEffects = 0 in {
|
||||
def DEC16r_alt : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"dec{w}\t$dst", [], IIC_UNARY_REG>,
|
||||
"dec{w}\t$dst", []>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def DEC32r_alt : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"dec{l}\t$dst", [], IIC_UNARY_REG>,
|
||||
"dec{l}\t$dst", []>,
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
} // CodeSize = 1, hasSideEffects = 0
|
||||
} // Constraints = "$src1 = $dst", SchedRW
|
||||
|
|
@ -540,18 +512,18 @@ let CodeSize = 2, SchedRW = [WriteALURMW] in {
|
|||
let Predicates = [UseIncDec] in {
|
||||
def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
|
||||
[(store (add (loadi8 addr:$dst), -1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
||||
(implicit EFLAGS)]>;
|
||||
def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
|
||||
[(store (add (loadi16 addr:$dst), -1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize16;
|
||||
(implicit EFLAGS)]>, OpSize16;
|
||||
def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
|
||||
[(store (add (loadi32 addr:$dst), -1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize32;
|
||||
(implicit EFLAGS)]>, OpSize32;
|
||||
} // Predicates
|
||||
let Predicates = [UseIncDec, In64BitMode] in {
|
||||
def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
|
||||
[(store (add (loadi64 addr:$dst), -1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
||||
(implicit EFLAGS)]>;
|
||||
} // Predicates
|
||||
} // CodeSize = 2, SchedRW
|
||||
} // Defs = [EFLAGS]
|
||||
|
|
@ -649,13 +621,11 @@ def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,
|
|||
/// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations)
|
||||
/// or 1 (for i16,i32,i64 operations).
|
||||
class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
|
||||
string mnemonic, string args, list<dag> pattern,
|
||||
InstrItinClass itin = IIC_BIN_NONMEM>
|
||||
string mnemonic, string args, list<dag> pattern>
|
||||
: I<{opcode{7}, opcode{6}, opcode{5}, opcode{4},
|
||||
opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode },
|
||||
f, outs, ins,
|
||||
!strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern,
|
||||
itin> {
|
||||
!strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> {
|
||||
|
||||
// Infer instruction prefixes from type info.
|
||||
let OpSize = typeinfo.OpSize;
|
||||
|
|
@ -664,10 +634,10 @@ class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
|
|||
|
||||
// BinOpRR - Instructions like "add reg, reg, reg".
|
||||
class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
||||
dag outlist, list<dag> pattern, InstrItinClass itin>
|
||||
dag outlist, list<dag> pattern>
|
||||
: ITy<opcode, MRMDestReg, typeinfo, outlist,
|
||||
(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
|
||||
mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
|
||||
mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
|
||||
Sched<[WriteALU]>;
|
||||
|
||||
// BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has
|
||||
|
|
@ -676,8 +646,7 @@ class BinOpRR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|||
SDPatternOperator opnode>
|
||||
: BinOpRR<opcode, mnemonic, typeinfo, (outs),
|
||||
[(set EFLAGS,
|
||||
(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
|
||||
IIC_BIN_NONMEM>;
|
||||
(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
|
||||
|
||||
// BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has
|
||||
// both a regclass and EFLAGS as a result.
|
||||
|
|
@ -685,8 +654,7 @@ class BinOpRR_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|||
SDNode opnode>
|
||||
: BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
|
||||
[(set typeinfo.RegClass:$dst, EFLAGS,
|
||||
(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
|
||||
IIC_BIN_NONMEM>;
|
||||
(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
|
||||
|
||||
// BinOpRR_RFF - Instructions like "adc reg, reg, reg", where the pattern has
|
||||
// both a regclass and EFLAGS as a result, and has EFLAGS as input.
|
||||
|
|
@ -695,15 +663,14 @@ class BinOpRR_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|||
: BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
|
||||
[(set typeinfo.RegClass:$dst, EFLAGS,
|
||||
(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
|
||||
EFLAGS))], IIC_BIN_CARRY_NONMEM>;
|
||||
EFLAGS))]>;
|
||||
|
||||
// BinOpRR_Rev - Instructions like "add reg, reg, reg" (reversed encoding).
|
||||
class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
||||
InstrItinClass itin = IIC_BIN_NONMEM>
|
||||
class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
|
||||
: ITy<opcode, MRMSrcReg, typeinfo,
|
||||
(outs typeinfo.RegClass:$dst),
|
||||
(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
|
||||
mnemonic, "{$src2, $dst|$dst, $src2}", [], itin>,
|
||||
mnemonic, "{$src2, $dst|$dst, $src2}", []>,
|
||||
Sched<[WriteALU]> {
|
||||
// The disassembler should know about this, but not the asmparser.
|
||||
let isCodeGenOnly = 1;
|
||||
|
|
@ -713,13 +680,13 @@ class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|||
|
||||
// BinOpRR_RDD_Rev - Instructions like "adc reg, reg, reg" (reversed encoding).
|
||||
class BinOpRR_RFF_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
|
||||
: BinOpRR_Rev<opcode, mnemonic, typeinfo, IIC_BIN_CARRY_NONMEM>;
|
||||
: BinOpRR_Rev<opcode, mnemonic, typeinfo>;
|
||||
|
||||
// BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding).
|
||||
class BinOpRR_F_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
|
||||
: ITy<opcode, MRMSrcReg, typeinfo, (outs),
|
||||
(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
|
||||
mnemonic, "{$src2, $src1|$src1, $src2}", [], IIC_BIN_NONMEM>,
|
||||
mnemonic, "{$src2, $src1|$src1, $src2}", []>,
|
||||
Sched<[WriteALU]> {
|
||||
// The disassembler should know about this, but not the asmparser.
|
||||
let isCodeGenOnly = 1;
|
||||
|
|
@ -729,11 +696,10 @@ class BinOpRR_F_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
|
|||
|
||||
// BinOpRM - Instructions like "add reg, reg, [mem]".
|
||||
class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
||||
dag outlist, list<dag> pattern,
|
||||
InstrItinClass itin = IIC_BIN_MEM>
|
||||
dag outlist, list<dag> pattern>
|
||||
: ITy<opcode, MRMSrcMem, typeinfo, outlist,
|
||||
(ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
|
||||
mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
|
||||
mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
|
||||
Sched<[WriteALULd, ReadAfterLd]>;
|
||||
|
||||
// BinOpRM_F - Instructions like "cmp reg, [mem]".
|
||||
|
|
@ -756,15 +722,14 @@ class BinOpRM_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|||
: BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
|
||||
[(set typeinfo.RegClass:$dst, EFLAGS,
|
||||
(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2),
|
||||
EFLAGS))], IIC_BIN_CARRY_MEM>;
|
||||
EFLAGS))]>;
|
||||
|
||||
// BinOpRI - Instructions like "add reg, reg, imm".
|
||||
class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
||||
Format f, dag outlist, list<dag> pattern,
|
||||
InstrItinClass itin = IIC_BIN_NONMEM>
|
||||
Format f, dag outlist, list<dag> pattern>
|
||||
: ITy<opcode, f, typeinfo, outlist,
|
||||
(ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
|
||||
mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
|
||||
mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
|
||||
Sched<[WriteALU]> {
|
||||
let ImmT = typeinfo.ImmEncoding;
|
||||
}
|
||||
|
|
@ -788,15 +753,14 @@ class BinOpRI_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|||
: BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
|
||||
[(set typeinfo.RegClass:$dst, EFLAGS,
|
||||
(opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2,
|
||||
EFLAGS))], IIC_BIN_CARRY_NONMEM>;
|
||||
EFLAGS))]>;
|
||||
|
||||
// BinOpRI8 - Instructions like "add reg, reg, imm8".
|
||||
class BinOpRI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
||||
Format f, dag outlist, list<dag> pattern,
|
||||
InstrItinClass itin = IIC_BIN_NONMEM>
|
||||
Format f, dag outlist, list<dag> pattern>
|
||||
: ITy<opcode, f, typeinfo, outlist,
|
||||
(ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2),
|
||||
mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
|
||||
mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
|
||||
Sched<[WriteALU]> {
|
||||
let ImmT = Imm8; // Always 8-bit immediate.
|
||||
}
|
||||
|
|
@ -821,14 +785,14 @@ class BinOpRI8_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|||
: BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
|
||||
[(set typeinfo.RegClass:$dst, EFLAGS,
|
||||
(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2,
|
||||
EFLAGS))], IIC_BIN_CARRY_NONMEM>;
|
||||
EFLAGS))]>;
|
||||
|
||||
// BinOpMR - Instructions like "add [mem], reg".
|
||||
class BinOpMR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_BIN_MEM>
|
||||
list<dag> pattern>
|
||||
: ITy<opcode, MRMDestMem, typeinfo,
|
||||
(outs), (ins typeinfo.MemOperand:$dst, typeinfo.RegClass:$src),
|
||||
mnemonic, "{$src, $dst|$dst, $src}", pattern, itin>;
|
||||
mnemonic, "{$src, $dst|$dst, $src}", pattern>;
|
||||
|
||||
// BinOpMR_RMW - Instructions like "add [mem], reg".
|
||||
class BinOpMR_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
||||
|
|
@ -843,8 +807,7 @@ class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|||
: BinOpMR<opcode, mnemonic, typeinfo,
|
||||
[(store (opnode (load addr:$dst), typeinfo.RegClass:$src, EFLAGS),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)], IIC_BIN_CARRY_MEM>,
|
||||
Sched<[WriteALURMW]>;
|
||||
(implicit EFLAGS)]>, Sched<[WriteALURMW]>;
|
||||
|
||||
// BinOpMR_F - Instructions like "cmp [mem], reg".
|
||||
class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
||||
|
|
@ -857,11 +820,10 @@ class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|||
|
||||
// BinOpMI - Instructions like "add [mem], imm".
|
||||
class BinOpMI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
||||
Format f, list<dag> pattern,
|
||||
InstrItinClass itin = IIC_BIN_MEM>
|
||||
Format f, list<dag> pattern>
|
||||
: ITy<opcode, f, typeinfo,
|
||||
(outs), (ins typeinfo.MemOperand:$dst, typeinfo.ImmOperand:$src),
|
||||
mnemonic, "{$src, $dst|$dst, $src}", pattern, itin> {
|
||||
mnemonic, "{$src, $dst|$dst, $src}", pattern> {
|
||||
let ImmT = typeinfo.ImmEncoding;
|
||||
}
|
||||
|
||||
|
|
@ -878,8 +840,7 @@ class BinOpMI_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|||
: BinOpMI<opcode, mnemonic, typeinfo, f,
|
||||
[(store (opnode (typeinfo.VT (load addr:$dst)),
|
||||
typeinfo.ImmOperator:$src, EFLAGS), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_BIN_CARRY_MEM>,
|
||||
Sched<[WriteALURMW]>;
|
||||
(implicit EFLAGS)]>, Sched<[WriteALURMW]>;
|
||||
|
||||
// BinOpMI_F - Instructions like "cmp [mem], imm".
|
||||
class BinOpMI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
||||
|
|
@ -891,11 +852,10 @@ class BinOpMI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|||
|
||||
// BinOpMI8 - Instructions like "add [mem], imm8".
|
||||
class BinOpMI8<string mnemonic, X86TypeInfo typeinfo,
|
||||
Format f, list<dag> pattern,
|
||||
InstrItinClass itin = IIC_BIN_MEM>
|
||||
Format f, list<dag> pattern>
|
||||
: ITy<0x82, f, typeinfo,
|
||||
(outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src),
|
||||
mnemonic, "{$src, $dst|$dst, $src}", pattern, itin> {
|
||||
mnemonic, "{$src, $dst|$dst, $src}", pattern> {
|
||||
let ImmT = Imm8; // Always 8-bit immediate.
|
||||
}
|
||||
|
||||
|
|
@ -913,8 +873,7 @@ class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo,
|
|||
: BinOpMI8<mnemonic, typeinfo, f,
|
||||
[(store (opnode (load addr:$dst),
|
||||
typeinfo.Imm8Operator:$src, EFLAGS), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_BIN_CARRY_MEM>,
|
||||
Sched<[WriteALURMW]>;
|
||||
(implicit EFLAGS)]>, Sched<[WriteALURMW]>;
|
||||
|
||||
// BinOpMI8_F - Instructions like "cmp [mem], imm8".
|
||||
class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo,
|
||||
|
|
@ -926,11 +885,10 @@ class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo,
|
|||
|
||||
// BinOpAI - Instructions like "add %eax, %eax, imm", that imp-def EFLAGS.
|
||||
class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
||||
Register areg, string operands,
|
||||
InstrItinClass itin = IIC_BIN_NONMEM>
|
||||
Register areg, string operands>
|
||||
: ITy<opcode, RawFrm, typeinfo,
|
||||
(outs), (ins typeinfo.ImmOperand:$src),
|
||||
mnemonic, operands, [], itin>, Sched<[WriteALU]> {
|
||||
mnemonic, operands, []>, Sched<[WriteALU]> {
|
||||
let ImmT = typeinfo.ImmEncoding;
|
||||
let Uses = [areg];
|
||||
let Defs = [areg, EFLAGS];
|
||||
|
|
@ -941,8 +899,7 @@ class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|||
// and use EFLAGS.
|
||||
class BinOpAI_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
||||
Register areg, string operands>
|
||||
: BinOpAI<opcode, mnemonic, typeinfo, areg, operands,
|
||||
IIC_BIN_CARRY_NONMEM> {
|
||||
: BinOpAI<opcode, mnemonic, typeinfo, areg, operands> {
|
||||
let Uses = [areg, EFLAGS];
|
||||
}
|
||||
|
||||
|
|
@ -1281,12 +1238,12 @@ multiclass bmi_andn<string mnemonic, RegisterClass RC, X86MemOperand x86memop,
|
|||
PatFrag ld_frag> {
|
||||
def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
|
||||
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))],
|
||||
IIC_BIN_NONMEM>, Sched<[WriteALU]>;
|
||||
[(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>,
|
||||
Sched<[WriteALU]>;
|
||||
def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
|
||||
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set RC:$dst, EFLAGS,
|
||||
(X86and_flag (not RC:$src1), (ld_frag addr:$src2)))], IIC_BIN_MEM>,
|
||||
(X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>,
|
||||
Sched<[WriteALULd, ReadAfterLd]>;
|
||||
}
|
||||
|
||||
|
|
@ -1310,28 +1267,25 @@ let Predicates = [HasBMI], AddedComplexity = -6 in {
|
|||
//===----------------------------------------------------------------------===//
|
||||
// MULX Instruction
|
||||
//
|
||||
multiclass bmi_mulx<string mnemonic, RegisterClass RC, X86MemOperand x86memop,
|
||||
InstrItinClass itin_reg, InstrItinClass itin_mem> {
|
||||
multiclass bmi_mulx<string mnemonic, RegisterClass RC, X86MemOperand x86memop> {
|
||||
let hasSideEffects = 0 in {
|
||||
let isCommutable = 1 in
|
||||
def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
|
||||
!strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
|
||||
[], itin_reg>, T8XD, VEX_4V, Sched<[WriteIMul, WriteIMulH]>;
|
||||
[]>, T8XD, VEX_4V, Sched<[WriteIMul, WriteIMulH]>;
|
||||
|
||||
let mayLoad = 1 in
|
||||
def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src),
|
||||
!strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
|
||||
[], itin_mem>, T8XD, VEX_4V, Sched<[WriteIMulLd, WriteIMulH]>;
|
||||
[]>, T8XD, VEX_4V, Sched<[WriteIMulLd, WriteIMulH]>;
|
||||
}
|
||||
}
|
||||
|
||||
let Predicates = [HasBMI2] in {
|
||||
let Uses = [EDX] in
|
||||
defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, IIC_MUL32_REG,
|
||||
IIC_MUL32_MEM>;
|
||||
defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem>;
|
||||
let Uses = [RDX] in
|
||||
defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, IIC_MUL64_REG,
|
||||
IIC_MUL64_MEM>, VEX_W;
|
||||
defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem>, VEX_W;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -1344,26 +1298,22 @@ let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS],
|
|||
(ins GR32:$src1, GR32:$src2),
|
||||
"adcx{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, EFLAGS,
|
||||
(X86adc_flag GR32:$src1, GR32:$src2, EFLAGS))],
|
||||
IIC_BIN_CARRY_NONMEM>, T8PD;
|
||||
(X86adc_flag GR32:$src1, GR32:$src2, EFLAGS))]>, T8PD;
|
||||
def ADCX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst),
|
||||
(ins GR64:$src1, GR64:$src2),
|
||||
"adcx{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, EFLAGS,
|
||||
(X86adc_flag GR64:$src1, GR64:$src2, EFLAGS))],
|
||||
IIC_BIN_CARRY_NONMEM>, T8PD;
|
||||
(X86adc_flag GR64:$src1, GR64:$src2, EFLAGS))]>, T8PD;
|
||||
|
||||
// We don't have patterns for ADOX yet.
|
||||
let hasSideEffects = 0 in {
|
||||
def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst),
|
||||
(ins GR32:$src1, GR32:$src2),
|
||||
"adox{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[], IIC_BIN_CARRY_NONMEM>, T8XS;
|
||||
"adox{l}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
|
||||
|
||||
def ADOX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst),
|
||||
(ins GR64:$src1, GR64:$src2),
|
||||
"adox{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[], IIC_BIN_CARRY_NONMEM>, T8XS;
|
||||
"adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
|
||||
} // hasSideEffects = 0
|
||||
} // SchedRW
|
||||
|
||||
|
|
@ -1372,27 +1322,25 @@ let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS],
|
|||
(ins GR32:$src1, i32mem:$src2),
|
||||
"adcx{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, EFLAGS,
|
||||
(X86adc_flag GR32:$src1, (loadi32 addr:$src2), EFLAGS))],
|
||||
IIC_BIN_CARRY_MEM>, T8PD;
|
||||
(X86adc_flag GR32:$src1, (loadi32 addr:$src2), EFLAGS))]>,
|
||||
T8PD;
|
||||
|
||||
def ADCX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst),
|
||||
(ins GR64:$src1, i64mem:$src2),
|
||||
"adcx{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, EFLAGS,
|
||||
(X86adc_flag GR64:$src1, (loadi64 addr:$src2), EFLAGS))],
|
||||
IIC_BIN_CARRY_MEM>, T8PD;
|
||||
(X86adc_flag GR64:$src1, (loadi64 addr:$src2), EFLAGS))]>,
|
||||
T8PD;
|
||||
|
||||
// We don't have patterns for ADOX yet.
|
||||
let hasSideEffects = 0 in {
|
||||
def ADOX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst),
|
||||
(ins GR32:$src1, i32mem:$src2),
|
||||
"adox{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[], IIC_BIN_CARRY_MEM>, T8XS;
|
||||
"adox{l}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
|
||||
|
||||
def ADOX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst),
|
||||
(ins GR64:$src1, i64mem:$src2),
|
||||
"adox{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[], IIC_BIN_CARRY_MEM>, T8XS;
|
||||
"adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
|
||||
} // hasSideEffects = 0
|
||||
} // mayLoad = 1, SchedRW = [WriteALULd]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -46,12 +46,11 @@ let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP],
|
|||
let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in {
|
||||
def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs),
|
||||
(ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
|
||||
"#ADJCALLSTACKDOWN", [], IIC_ALU_NONMEM>,
|
||||
Requires<[NotLP64]>;
|
||||
"#ADJCALLSTACKDOWN", []>, Requires<[NotLP64]>;
|
||||
def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
"#ADJCALLSTACKUP",
|
||||
[(X86callseq_end timm:$amt1, timm:$amt2)],
|
||||
IIC_ALU_NONMEM>, Requires<[NotLP64]>;
|
||||
[(X86callseq_end timm:$amt1, timm:$amt2)]>,
|
||||
Requires<[NotLP64]>;
|
||||
}
|
||||
def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
|
||||
(ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>;
|
||||
|
|
@ -65,12 +64,11 @@ def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
|
|||
let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in {
|
||||
def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs),
|
||||
(ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
|
||||
"#ADJCALLSTACKDOWN",
|
||||
[], IIC_ALU_NONMEM>, Requires<[IsLP64]>;
|
||||
"#ADJCALLSTACKDOWN", []>, Requires<[IsLP64]>;
|
||||
def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
"#ADJCALLSTACKUP",
|
||||
[(X86callseq_end timm:$amt1, timm:$amt2)],
|
||||
IIC_ALU_NONMEM>, Requires<[IsLP64]>;
|
||||
[(X86callseq_end timm:$amt1, timm:$amt2)]>,
|
||||
Requires<[IsLP64]>;
|
||||
}
|
||||
def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
|
||||
(ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>;
|
||||
|
|
@ -148,10 +146,10 @@ def WIN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size),
|
|||
// frame register after register allocation.
|
||||
let Constraints = "$src = $dst", isPseudo = 1, Defs = [EFLAGS] in {
|
||||
def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
|
||||
"xorl\t$$FP, $src", [], IIC_BIN_NONMEM>,
|
||||
"xorl\t$$FP, $src", []>,
|
||||
Requires<[NotLP64]>, Sched<[WriteALU]>;
|
||||
def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src),
|
||||
"xorq\t$$FP $src", [], IIC_BIN_NONMEM>,
|
||||
"xorq\t$$FP $src", []>,
|
||||
Requires<[In64BitMode]>, Sched<[WriteALU]>;
|
||||
}
|
||||
|
||||
|
|
@ -273,7 +271,7 @@ def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), "", []>;
|
|||
let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
|
||||
isPseudo = 1, AddedComplexity = 10 in
|
||||
def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
|
||||
[(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
|
||||
[(set GR32:$dst, 0)]>, Sched<[WriteZero]>;
|
||||
|
||||
// Other widths can also make use of the 32-bit xor, which may have a smaller
|
||||
// encoding and avoid partial register updates.
|
||||
|
|
@ -290,9 +288,9 @@ let Predicates = [OptForSize, Not64BitMode],
|
|||
// which only require 3 bytes compared to MOV32ri which requires 5.
|
||||
let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in {
|
||||
def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
|
||||
[(set GR32:$dst, 1)], IIC_ALU_NONMEM>;
|
||||
[(set GR32:$dst, 1)]>;
|
||||
def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
|
||||
[(set GR32:$dst, -1)], IIC_ALU_NONMEM>;
|
||||
[(set GR32:$dst, -1)]>;
|
||||
}
|
||||
} // SchedRW
|
||||
|
||||
|
|
@ -305,10 +303,10 @@ let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5,
|
|||
SchedRW = [WriteALU] in {
|
||||
// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1.
|
||||
def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "",
|
||||
[(set GR32:$dst, i32immSExt8:$src)], IIC_ALU_NONMEM>,
|
||||
[(set GR32:$dst, i32immSExt8:$src)]>,
|
||||
Requires<[OptForMinSize, NotWin64WithoutFP]>;
|
||||
def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "",
|
||||
[(set GR64:$dst, i64immSExt8:$src)], IIC_ALU_NONMEM>,
|
||||
[(set GR64:$dst, i64immSExt8:$src)]>,
|
||||
Requires<[OptForMinSize, NotWin64WithoutFP]>;
|
||||
}
|
||||
|
||||
|
|
@ -592,9 +590,9 @@ let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in {
|
|||
// TODO: Get this to fold the constant into the instruction.
|
||||
let isCodeGenOnly = 1, Defs = [EFLAGS] in
|
||||
def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
|
||||
"or{l}\t{$zero, $dst|$dst, $zero}", [],
|
||||
IIC_ALU_MEM>, Requires<[Not64BitMode]>, OpSize32, LOCK,
|
||||
Sched<[WriteALULd, WriteRMW]>;
|
||||
"or{l}\t{$zero, $dst|$dst, $zero}", []>,
|
||||
Requires<[Not64BitMode]>, OpSize32, LOCK,
|
||||
Sched<[WriteALULd, WriteRMW]>;
|
||||
|
||||
let hasSideEffects = 1 in
|
||||
def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
|
||||
|
|
@ -615,89 +613,85 @@ def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
|
|||
MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
|
||||
!strconcat(mnemonic, "{b}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[(set EFLAGS, (Op addr:$dst, GR8:$src2))],
|
||||
IIC_ALU_NONMEM>, LOCK;
|
||||
[(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK;
|
||||
|
||||
def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
|
||||
RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
|
||||
MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
||||
!strconcat(mnemonic, "{w}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[(set EFLAGS, (Op addr:$dst, GR16:$src2))],
|
||||
IIC_ALU_NONMEM>, OpSize16, LOCK;
|
||||
[(set EFLAGS, (Op addr:$dst, GR16:$src2))]>,
|
||||
OpSize16, LOCK;
|
||||
|
||||
def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
|
||||
RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
|
||||
MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
||||
!strconcat(mnemonic, "{l}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[(set EFLAGS, (Op addr:$dst, GR32:$src2))],
|
||||
IIC_ALU_NONMEM>, OpSize32, LOCK;
|
||||
[(set EFLAGS, (Op addr:$dst, GR32:$src2))]>,
|
||||
OpSize32, LOCK;
|
||||
|
||||
def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
|
||||
RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
|
||||
MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
||||
!strconcat(mnemonic, "{q}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[(set EFLAGS, (Op addr:$dst, GR64:$src2))],
|
||||
IIC_ALU_NONMEM>, LOCK;
|
||||
[(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK;
|
||||
|
||||
def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
|
||||
ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
|
||||
ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
|
||||
!strconcat(mnemonic, "{b}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))],
|
||||
IIC_ALU_MEM>, LOCK;
|
||||
[(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK;
|
||||
|
||||
def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
|
||||
ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
|
||||
ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
|
||||
!strconcat(mnemonic, "{w}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))],
|
||||
IIC_ALU_MEM>, OpSize16, LOCK;
|
||||
[(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>,
|
||||
OpSize16, LOCK;
|
||||
|
||||
def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
|
||||
ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
|
||||
ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
|
||||
!strconcat(mnemonic, "{l}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))],
|
||||
IIC_ALU_MEM>, OpSize32, LOCK;
|
||||
[(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>,
|
||||
OpSize32, LOCK;
|
||||
|
||||
def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
|
||||
ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
|
||||
ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
|
||||
!strconcat(mnemonic, "{q}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))],
|
||||
IIC_ALU_MEM>, LOCK;
|
||||
[(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>,
|
||||
LOCK;
|
||||
|
||||
def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
|
||||
ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
|
||||
ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
|
||||
!strconcat(mnemonic, "{w}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))],
|
||||
IIC_ALU_MEM>, OpSize16, LOCK;
|
||||
[(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>,
|
||||
OpSize16, LOCK;
|
||||
|
||||
def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
|
||||
ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
|
||||
ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
|
||||
!strconcat(mnemonic, "{l}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))],
|
||||
IIC_ALU_MEM>, OpSize32, LOCK;
|
||||
[(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>,
|
||||
OpSize32, LOCK;
|
||||
|
||||
def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
|
||||
ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
|
||||
ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
|
||||
!strconcat(mnemonic, "{q}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))],
|
||||
IIC_ALU_MEM>, LOCK;
|
||||
|
||||
[(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>,
|
||||
LOCK;
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -714,20 +708,20 @@ let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
|
|||
SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
|
||||
!strconcat(mnemonic, "{b}\t$dst"),
|
||||
[(set EFLAGS, (!cast<PatFrag>(frag # "_8") addr:$dst))],
|
||||
IIC_UNARY_MEM>, LOCK;
|
||||
[(set EFLAGS, (!cast<PatFrag>(frag # "_8") addr:$dst))]>,
|
||||
LOCK;
|
||||
def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
|
||||
!strconcat(mnemonic, "{w}\t$dst"),
|
||||
[(set EFLAGS, (!cast<PatFrag>(frag # "_16") addr:$dst))],
|
||||
IIC_UNARY_MEM>, OpSize16, LOCK;
|
||||
[(set EFLAGS, (!cast<PatFrag>(frag # "_16") addr:$dst))]>,
|
||||
OpSize16, LOCK;
|
||||
def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
|
||||
!strconcat(mnemonic, "{l}\t$dst"),
|
||||
[(set EFLAGS, (!cast<PatFrag>(frag # "_32") addr:$dst))],
|
||||
IIC_UNARY_MEM>, OpSize32, LOCK;
|
||||
[(set EFLAGS, (!cast<PatFrag>(frag # "_32") addr:$dst))]>,
|
||||
OpSize32, LOCK;
|
||||
def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
|
||||
!strconcat(mnemonic, "{q}\t$dst"),
|
||||
[(set EFLAGS, (!cast<PatFrag>(frag # "_64") addr:$dst))],
|
||||
IIC_UNARY_MEM>, LOCK;
|
||||
[(set EFLAGS, (!cast<PatFrag>(frag # "_64") addr:$dst))]>,
|
||||
LOCK;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1324,16 +1318,13 @@ let isConvertibleToThreeAddress = 1,
|
|||
let isCommutable = 1 in {
|
||||
def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
||||
"", // orw/addw REG, REG
|
||||
[(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))],
|
||||
IIC_BIN_NONMEM>;
|
||||
[(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
|
||||
def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
||||
"", // orl/addl REG, REG
|
||||
[(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))],
|
||||
IIC_BIN_NONMEM>;
|
||||
[(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
|
||||
def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"", // orq/addq REG, REG
|
||||
[(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))],
|
||||
IIC_BIN_NONMEM>;
|
||||
[(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
|
||||
} // isCommutable
|
||||
|
||||
// NOTE: These are order specific, we want the ri8 forms to be listed
|
||||
|
|
@ -1342,36 +1333,30 @@ def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|||
def ADD16ri8_DB : I<0, Pseudo,
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
|
||||
"", // orw/addw REG, imm8
|
||||
[(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))],
|
||||
IIC_BIN_NONMEM>;
|
||||
[(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
|
||||
def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
|
||||
"", // orw/addw REG, imm
|
||||
[(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))],
|
||||
IIC_BIN_NONMEM>;
|
||||
[(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
|
||||
|
||||
def ADD32ri8_DB : I<0, Pseudo,
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
|
||||
"", // orl/addl REG, imm8
|
||||
[(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))],
|
||||
IIC_BIN_NONMEM>;
|
||||
[(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
|
||||
def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
|
||||
"", // orl/addl REG, imm
|
||||
[(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))],
|
||||
IIC_BIN_NONMEM>;
|
||||
[(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
|
||||
|
||||
|
||||
def ADD64ri8_DB : I<0, Pseudo,
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
|
||||
"", // orq/addq REG, imm8
|
||||
[(set GR64:$dst, (or_is_add GR64:$src1,
|
||||
i64immSExt8:$src2))],
|
||||
IIC_BIN_NONMEM>;
|
||||
i64immSExt8:$src2))]>;
|
||||
def ADD64ri32_DB : I<0, Pseudo,
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
|
||||
"", // orq/addq REG, imm
|
||||
[(set GR64:$dst, (or_is_add GR64:$src1,
|
||||
i64immSExt32:$src2))],
|
||||
IIC_BIN_NONMEM>;
|
||||
i64immSExt32:$src2))]>;
|
||||
}
|
||||
} // AddedComplexity, SchedRW
|
||||
|
||||
|
|
|
|||
|
|
@ -2282,12 +2282,12 @@ multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
|
|||
RegisterClass RC, X86MemOperand x86memop> {
|
||||
let hasSideEffects = 0 in {
|
||||
def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
|
||||
!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
|
||||
[], IIC_UNARY_REG>, T8PS, VEX_4V, Sched<[WriteALU]>;
|
||||
!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
|
||||
T8PS, VEX_4V, Sched<[WriteALU]>;
|
||||
let mayLoad = 1 in
|
||||
def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
|
||||
!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
|
||||
[], IIC_UNARY_MEM>, T8PS, VEX_4V, Sched<[WriteALULd]>;
|
||||
!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
|
||||
T8PS, VEX_4V, Sched<[WriteALULd]>;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2327,12 +2327,12 @@ multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
|
|||
PatFrag ld_frag, X86FoldableSchedWrite Sched> {
|
||||
def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
|
||||
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)], IIC_BIN_NONMEM>,
|
||||
[(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
|
||||
T8PS, VEX, Sched<[Sched]>;
|
||||
def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
|
||||
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
|
||||
(implicit EFLAGS)], IIC_BIN_MEM>, T8PS, VEX,
|
||||
(implicit EFLAGS)]>, T8PS, VEX,
|
||||
Sched<[Sched.Folded,
|
||||
// x86memop:$src1
|
||||
ReadDefault, ReadDefault, ReadDefault, ReadDefault,
|
||||
|
|
@ -2448,12 +2448,12 @@ multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
|
|||
PatFrag ld_frag> {
|
||||
def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
|
||||
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set RC:$dst, (Int RC:$src1, RC:$src2))], IIC_BIN_NONMEM>,
|
||||
[(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
|
||||
VEX_4V, Sched<[WriteALU]>;
|
||||
def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
|
||||
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))],
|
||||
IIC_BIN_MEM>, VEX_4V, Sched<[WriteALULd, ReadAfterLd]>;
|
||||
[(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>,
|
||||
VEX_4V, Sched<[WriteALULd, ReadAfterLd]>;
|
||||
}
|
||||
|
||||
let Predicates = [HasBMI2] in {
|
||||
|
|
@ -2479,14 +2479,14 @@ multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
|
|||
def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
|
||||
[(set RC:$dst, (Int RC:$src1, immoperator:$cntl))],
|
||||
IIC_BIN_NONMEM>, XOP, XOPA, Sched<[WriteALU]>;
|
||||
[(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
|
||||
XOP, XOPA, Sched<[WriteALU]>;
|
||||
def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
|
||||
(ins x86memop:$src1, immtype:$cntl),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
|
||||
[(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))],
|
||||
IIC_BIN_MEM>, XOP, XOPA, Sched<[WriteALULd]>;
|
||||
[(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
|
||||
XOP, XOPA, Sched<[WriteALULd]>;
|
||||
}
|
||||
|
||||
defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr{l}", i32mem, loadi32,
|
||||
|
|
@ -2501,12 +2501,12 @@ multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
|
|||
X86MemOperand x86memop> {
|
||||
let hasSideEffects = 0 in {
|
||||
def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
|
||||
!strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
|
||||
[], IIC_BIN_NONMEM>, XOP_4V, XOP9, Sched<[WriteALU]>;
|
||||
!strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>,
|
||||
XOP_4V, XOP9, Sched<[WriteALU]>;
|
||||
let mayLoad = 1 in
|
||||
def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
|
||||
!strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
|
||||
[], IIC_BIN_MEM>, XOP_4V, XOP9, Sched<[WriteALULd]>;
|
||||
!strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>,
|
||||
XOP_4V, XOP9, Sched<[WriteALULd]>;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -170,66 +170,6 @@ def WriteNop : SchedWrite;
|
|||
// Instruction Itinerary classes used for X86
|
||||
def IIC_ALU_MEM : InstrItinClass;
|
||||
def IIC_ALU_NONMEM : InstrItinClass;
|
||||
def IIC_LEA : InstrItinClass;
|
||||
def IIC_LEA_16 : InstrItinClass;
|
||||
def IIC_MUL8_MEM : InstrItinClass;
|
||||
def IIC_MUL8_REG : InstrItinClass;
|
||||
def IIC_MUL16_MEM : InstrItinClass;
|
||||
def IIC_MUL16_REG : InstrItinClass;
|
||||
def IIC_MUL32_MEM : InstrItinClass;
|
||||
def IIC_MUL32_REG : InstrItinClass;
|
||||
def IIC_MUL64_MEM : InstrItinClass;
|
||||
def IIC_MUL64_REG : InstrItinClass;
|
||||
// imul by al, ax, eax, tax
|
||||
def IIC_IMUL8_MEM : InstrItinClass;
|
||||
def IIC_IMUL8_REG : InstrItinClass;
|
||||
def IIC_IMUL16_MEM : InstrItinClass;
|
||||
def IIC_IMUL16_REG : InstrItinClass;
|
||||
def IIC_IMUL32_MEM : InstrItinClass;
|
||||
def IIC_IMUL32_REG : InstrItinClass;
|
||||
def IIC_IMUL64_MEM : InstrItinClass;
|
||||
def IIC_IMUL64_REG : InstrItinClass;
|
||||
// imul reg by reg|mem
|
||||
def IIC_IMUL16_RM : InstrItinClass;
|
||||
def IIC_IMUL16_RR : InstrItinClass;
|
||||
def IIC_IMUL32_RM : InstrItinClass;
|
||||
def IIC_IMUL32_RR : InstrItinClass;
|
||||
def IIC_IMUL64_RM : InstrItinClass;
|
||||
def IIC_IMUL64_RR : InstrItinClass;
|
||||
// imul reg = reg/mem * imm
|
||||
def IIC_IMUL16_RMI : InstrItinClass;
|
||||
def IIC_IMUL16_RRI : InstrItinClass;
|
||||
def IIC_IMUL32_RMI : InstrItinClass;
|
||||
def IIC_IMUL32_RRI : InstrItinClass;
|
||||
def IIC_IMUL64_RMI : InstrItinClass;
|
||||
def IIC_IMUL64_RRI : InstrItinClass;
|
||||
// div
|
||||
def IIC_DIV8_MEM : InstrItinClass;
|
||||
def IIC_DIV8_REG : InstrItinClass;
|
||||
def IIC_DIV16_MEM : InstrItinClass;
|
||||
def IIC_DIV16_REG : InstrItinClass;
|
||||
def IIC_DIV32_MEM : InstrItinClass;
|
||||
def IIC_DIV32_REG : InstrItinClass;
|
||||
def IIC_DIV64_MEM : InstrItinClass;
|
||||
def IIC_DIV64_REG : InstrItinClass;
|
||||
// idiv
|
||||
def IIC_IDIV8_MEM : InstrItinClass;
|
||||
def IIC_IDIV8_REG : InstrItinClass;
|
||||
def IIC_IDIV16_MEM : InstrItinClass;
|
||||
def IIC_IDIV16_REG : InstrItinClass;
|
||||
def IIC_IDIV32_MEM : InstrItinClass;
|
||||
def IIC_IDIV32_REG : InstrItinClass;
|
||||
def IIC_IDIV64_MEM : InstrItinClass;
|
||||
def IIC_IDIV64_REG : InstrItinClass;
|
||||
// neg/not/inc/dec
|
||||
def IIC_UNARY_REG : InstrItinClass;
|
||||
def IIC_UNARY_MEM : InstrItinClass;
|
||||
// add/sub/and/or/xor/sbc/cmp/test
|
||||
def IIC_BIN_MEM : InstrItinClass;
|
||||
def IIC_BIN_NONMEM : InstrItinClass;
|
||||
// adc/sbc
|
||||
def IIC_BIN_CARRY_MEM : InstrItinClass;
|
||||
def IIC_BIN_CARRY_NONMEM : InstrItinClass;
|
||||
|
||||
// SSE scalar/parallel binary operations
|
||||
def IIC_SSE_ALU_F32S_RR : InstrItinClass;
|
||||
|
|
@ -379,7 +319,7 @@ def IIC_SSE_ROUNDPD_REG : InstrItinClass;
|
|||
def IIC_SSE_ROUNDPD_MEM : InstrItinClass;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Processor instruction itineraries.
|
||||
// Generic Processor Scheduler Models.
|
||||
|
||||
// IssueWidth is analogous to the number of decode units. Core and its
|
||||
// descendents, including Nehalem and SandyBridge have 4 decoders.
|
||||
|
|
|
|||
Loading…
Reference in New Issue