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Match another form of eqv 

llvm-svn: 21413
This commit is contained in:
Chris Lattner 2005-04-21 21:09:11 +00:00
parent df586aa20e
commit 3590ef1164
1 changed files with 6 additions and 1 deletions
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7
llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
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@ -1899,7 +1899,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
BuildMI(BB, PPC::EQV, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
}
// Check for NOT, NOR, and NAND: xor (copy, or, and), -1
// Check for NOT, NOR, EQV, and NAND: xor (copy, or, xor, and), -1
if (N.getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(1))->isAllOnesValue()) {
switch(N.getOperand(0).getOpcode()) {
@ -1913,6 +1913,11 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
BuildMI(BB, PPC::NAND, 2, Result).addReg(Tmp1).addReg(Tmp2);
break;
case ISD::XOR:
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
BuildMI(BB, PPC::EQV, 2, Result).addReg(Tmp1).addReg(Tmp2);
break;
default:
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::NOR, 2, Result).addReg(Tmp1).addReg(Tmp1);