forked from OSchip/llvm-project
MC/X86: Error out if we see a non-constant FK_Data_1 or FK_Data_2 fixup, since
we don't currently support relaxing them. llvm-svn: 103195
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@ -12,6 +12,7 @@
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#include "X86FixupKinds.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSectionMachO.h"
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@ -88,9 +89,20 @@ static unsigned getRelaxedOpcode(unsigned Op) {
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bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst,
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const SmallVectorImpl<MCAsmFixup> &Fixups) const {
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// Check for a 1byte pcrel fixup, and enforce that we would know how to relax
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// this instruction.
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for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
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// We don't support relaxing anything else currently. Make sure we error out
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// if we see a non-constant 1 or 2 byte fixup.
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//
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// FIXME: We should need to check this here, this is better checked in the
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// object writer which should be verifying that any final relocations match
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// the expected fixup. However, that code is more complicated and hasn't
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// been written yet. See the FIXMEs in MachObjectWriter.cpp.
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if ((Fixups[i].Kind == FK_Data_1 || Fixups[i].Kind == FK_Data_2) &&
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!isa<MCConstantExpr>(Fixups[i].Value))
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report_fatal_error("unexpected small fixup with a non-constant operand!");
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// Check for a 1byte pcrel fixup, and enforce that we would know how to
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// relax this instruction.
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if (unsigned(Fixups[i].Kind) == X86::reloc_pcrel_1byte) {
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assert(getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode());
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return true;
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