forked from OSchip/llvm-project
GlobalISel: support same ConstantExprs as Instructions.
It's more than just inttoptr, but the others can't be tested until we have support for non-trivial constants (they currently get unavoidably folded to a ConstantInt). llvm-svn: 278303
This commit is contained in:
Tim Northover
parent
1ae68cdee7
commit
357f1be2ca
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@ -109,47 +109,128 @@ private:
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/// Translate an LLVM bitcast into generic IR. Either a COPY or a G_BITCAST is
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/// emitted.
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bool translateBitCast(const CastInst &CI);
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bool translateBitCast(const User &U);
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/// Translate an LLVM load instruction into generic IR.
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bool translateLoad(const LoadInst &LI);
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bool translateLoad(const User &U);
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/// Translate an LLVM store instruction into generic IR.
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bool translateStore(const StoreInst &SI);
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bool translateStore(const User &U);
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/// Translate call instruction.
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/// \pre \p Inst is a call instruction.
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bool translateCall(const CallInst &Inst);
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/// \pre \p U is a call instruction.
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bool translateCall(const User &U);
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/// Translate one of LLVM's cast instructions into MachineInstrs, with the
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/// given generic Opcode.
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bool translateCast(unsigned Opcode, const CastInst &CI);
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bool translateCast(unsigned Opcode, const User &U);
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/// Translate static alloca instruction (i.e. one of constant size and in the
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/// first basic block).
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bool translateStaticAlloca(const AllocaInst &Inst);
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/// Translate a phi instruction.
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bool translatePhi(const PHINode &PI);
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bool translatePHI(const User &U);
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/// Add remaining operands onto phis we've translated. Executed after all
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/// MachineBasicBlocks for the function have been created.
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void finishPendingPhis();
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/// Translate \p Inst into a binary operation \p Opcode.
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/// \pre \p Inst is a binary operation.
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bool translateBinaryOp(unsigned Opcode, const BinaryOperator &Inst);
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/// \pre \p U is a binary operation.
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bool translateBinaryOp(unsigned Opcode, const User &U);
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/// Translate branch (br) instruction.
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/// \pre \p Inst is a branch instruction.
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bool translateBr(const BranchInst &Inst);
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/// \pre \p U is a branch instruction.
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bool translateBr(const User &U);
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bool translateAdd(const User &U) {
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return translateBinaryOp(TargetOpcode::G_ADD, U);
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}
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bool translateSub(const User &U) {
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return translateBinaryOp(TargetOpcode::G_SUB, U);
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}
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bool translateAnd(const User &U) {
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return translateBinaryOp(TargetOpcode::G_AND, U);
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}
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bool translateMul(const User &U) {
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return translateBinaryOp(TargetOpcode::G_MUL, U);
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}
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bool translateOr(const User &U) {
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return translateBinaryOp(TargetOpcode::G_OR, U);
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}
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bool translateXor(const User &U) {
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return translateBinaryOp(TargetOpcode::G_XOR, U);
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}
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bool translateAlloca(const User &U) {
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return translateStaticAlloca(cast<AllocaInst>(U));
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}
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bool translateIntToPtr(const User &U) {
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return translateCast(TargetOpcode::G_INTTOPTR, U);
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}
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bool translatePtrToInt(const User &U) {
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return translateCast(TargetOpcode::G_PTRTOINT, U);
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}
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bool translateTrunc(const User &U) {
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return translateCast(TargetOpcode::G_TRUNC, U);
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}
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bool translateUnreachable(const User &U) { return true; }
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/// Translate return (ret) instruction.
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/// The target needs to implement CallLowering::lowerReturn for
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/// this to succeed.
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/// \pre \p Inst is a return instruction.
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bool translateReturn(const ReturnInst &Inst);
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/// \pre \p U is a return instruction.
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bool translateRet(const User &U);
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// Stubs to keep the compiler happy while we implement the rest of the
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// translation.
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bool translateSwitch(const User &U) { return false; }
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bool translateIndirectBr(const User &U) { return false; }
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bool translateInvoke(const User &U) { return false; }
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bool translateResume(const User &U) { return false; }
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bool translateCleanupRet(const User &U) { return false; }
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bool translateCatchRet(const User &U) { return false; }
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bool translateCatchSwitch(const User &U) { return false; }
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bool translateFAdd(const User &U) { return false; }
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bool translateFSub(const User &U) { return false; }
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bool translateFMul(const User &U) { return false; }
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bool translateUDiv(const User &U) { return false; }
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bool translateSDiv(const User &U) { return false; }
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bool translateFDiv(const User &U) { return false; }
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bool translateURem(const User &U) { return false; }
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bool translateSRem(const User &U) { return false; }
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bool translateFRem(const User &U) { return false; }
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bool translateShl(const User &U) { return false; }
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bool translateLShr(const User &U) { return false; }
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bool translateAShr(const User &U) { return false; }
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bool translateGetElementPtr(const User &U) { return false; }
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bool translateFence(const User &U) { return false; }
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bool translateAtomicCmpXchg(const User &U) { return false; }
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bool translateAtomicRMW(const User &U) { return false; }
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bool translateSExt(const User &U) { return false; }
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bool translateZExt(const User &U) { return false; }
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bool translateFPToUI(const User &U) { return false; }
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bool translateFPToSI(const User &U) { return false; }
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bool translateUIToFP(const User &U) { return false; }
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bool translateSIToFP(const User &U) { return false; }
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bool translateFPTrunc(const User &U) { return false; }
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bool translateFPExt(const User &U) { return false; }
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bool translateAddrSpaceCast(const User &U) { return false; }
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bool translateCleanupPad(const User &U) { return false; }
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bool translateCatchPad(const User &U) { return false; }
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bool translateICmp(const User &U) { return false; }
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bool translateFCmp(const User &U) { return false; }
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bool translateSelect(const User &U) { return false; }
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bool translateUserOp1(const User &U) { return false; }
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bool translateUserOp2(const User &U) { return false; }
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bool translateVAArg(const User &U) { return false; }
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bool translateExtractElement(const User &U) { return false; }
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bool translateInsertElement(const User &U) { return false; }
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bool translateShuffleVector(const User &U) { return false; }
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bool translateExtractValue(const User &U) { return false; }
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bool translateInsertValue(const User &U) { return false; }
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bool translateLandingPad(const User &U) { return false; }
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/// @}
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// Builder for machine instruction a la IRBuilder.
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@ -84,25 +84,25 @@ MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock &BB) {
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return *MBB;
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}
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bool IRTranslator::translateBinaryOp(unsigned Opcode,
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const BinaryOperator &Inst) {
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bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U) {
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// FIXME: handle signed/unsigned wrapping flags.
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// Get or create a virtual register for each value.
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// Unless the value is a Constant => loadimm cst?
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// or inline constant each time?
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// Creation of a virtual register needs to have a size.
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unsigned Op0 = getOrCreateVReg(*Inst.getOperand(0));
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unsigned Op1 = getOrCreateVReg(*Inst.getOperand(1));
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unsigned Res = getOrCreateVReg(Inst);
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MIRBuilder.buildInstr(Opcode, LLT{*Inst.getType()})
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unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
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unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
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unsigned Res = getOrCreateVReg(U);
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MIRBuilder.buildInstr(Opcode, LLT{*U.getType()})
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.addDef(Res)
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.addUse(Op0)
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.addUse(Op1);
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return true;
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}
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bool IRTranslator::translateReturn(const ReturnInst &RI) {
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bool IRTranslator::translateRet(const User &U) {
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const ReturnInst &RI = cast<ReturnInst>(U);
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const Value *Ret = RI.getReturnValue();
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// The target may mess up with the insertion point, but
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// this is not important as a return is the last instruction
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@ -110,7 +110,8 @@ bool IRTranslator::translateReturn(const ReturnInst &RI) {
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return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
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}
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bool IRTranslator::translateBr(const BranchInst &BrInst) {
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bool IRTranslator::translateBr(const User &U) {
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const BranchInst &BrInst = cast<BranchInst>(U);
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unsigned Succ = 0;
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if (!BrInst.isUnconditional()) {
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// We want a G_BRCOND to the true BB followed by an unconditional branch.
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@ -131,7 +132,8 @@ bool IRTranslator::translateBr(const BranchInst &BrInst) {
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return true;
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}
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bool IRTranslator::translateLoad(const LoadInst &LI) {
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bool IRTranslator::translateLoad(const User &U) {
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const LoadInst &LI = cast<LoadInst>(U);
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assert(LI.isSimple() && "only simple loads are supported at the moment");
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MachineFunction &MF = MIRBuilder.getMF();
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@ -147,7 +149,8 @@ bool IRTranslator::translateLoad(const LoadInst &LI) {
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return true;
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}
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bool IRTranslator::translateStore(const StoreInst &SI) {
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bool IRTranslator::translateStore(const User &U) {
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const StoreInst &SI = cast<StoreInst>(U);
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assert(SI.isSimple() && "only simple loads are supported at the moment");
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MachineFunction &MF = MIRBuilder.getMF();
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@ -164,28 +167,30 @@ bool IRTranslator::translateStore(const StoreInst &SI) {
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return true;
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}
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bool IRTranslator::translateBitCast(const CastInst &CI) {
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if (LLT{*CI.getDestTy()} == LLT{*CI.getSrcTy()}) {
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unsigned &Reg = ValToVReg[&CI];
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bool IRTranslator::translateBitCast(const User &U) {
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if (LLT{*U.getOperand(0)->getType()} == LLT{*U.getType()}) {
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unsigned &Reg = ValToVReg[&U];
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if (Reg)
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MIRBuilder.buildCopy(Reg, getOrCreateVReg(*CI.getOperand(0)));
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MIRBuilder.buildCopy(Reg, getOrCreateVReg(*U.getOperand(0)));
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else
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Reg = getOrCreateVReg(*CI.getOperand(0));
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Reg = getOrCreateVReg(*U.getOperand(0));
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return true;
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}
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return translateCast(TargetOpcode::G_BITCAST, CI);
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return translateCast(TargetOpcode::G_BITCAST, U);
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}
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bool IRTranslator::translateCast(unsigned Opcode, const CastInst &CI) {
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unsigned Op = getOrCreateVReg(*CI.getOperand(0));
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unsigned Res = getOrCreateVReg(CI);
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MIRBuilder.buildInstr(Opcode, {LLT{*CI.getDestTy()}, LLT{*CI.getSrcTy()}})
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bool IRTranslator::translateCast(unsigned Opcode, const User &U) {
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unsigned Op = getOrCreateVReg(*U.getOperand(0));
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unsigned Res = getOrCreateVReg(U);
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MIRBuilder
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.buildInstr(Opcode, {LLT{*U.getType()}, LLT{*U.getOperand(0)->getType()}})
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.addDef(Res)
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.addUse(Op);
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return true;
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}
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bool IRTranslator::translateCall(const CallInst &CI) {
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bool IRTranslator::translateCall(const User &U) {
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const CallInst &CI = cast<CallInst>(U);
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auto TII = MIRBuilder.getMF().getTarget().getIntrinsicInfo();
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const Function *F = CI.getCalledFunction();
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@ -246,7 +251,8 @@ bool IRTranslator::translateStaticAlloca(const AllocaInst &AI) {
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return true;
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}
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bool IRTranslator::translatePhi(const PHINode &PI) {
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bool IRTranslator::translatePHI(const User &U) {
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const PHINode &PI = cast<PHINode>(U);
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MachineInstrBuilder MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
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MIB.addDef(getOrCreateVReg(PI));
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@ -277,59 +283,11 @@ void IRTranslator::finishPendingPhis() {
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bool IRTranslator::translate(const Instruction &Inst) {
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MIRBuilder.setDebugLoc(Inst.getDebugLoc());
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switch(Inst.getOpcode()) {
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// Arithmetic operations.
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case Instruction::Add:
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return translateBinaryOp(TargetOpcode::G_ADD, cast<BinaryOperator>(Inst));
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case Instruction::Sub:
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return translateBinaryOp(TargetOpcode::G_SUB, cast<BinaryOperator>(Inst));
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// Bitwise operations.
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case Instruction::And:
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return translateBinaryOp(TargetOpcode::G_AND, cast<BinaryOperator>(Inst));
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case Instruction::Mul:
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return translateBinaryOp(TargetOpcode::G_MUL, cast<BinaryOperator>(Inst));
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case Instruction::Or:
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return translateBinaryOp(TargetOpcode::G_OR, cast<BinaryOperator>(Inst));
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case Instruction::Xor:
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return translateBinaryOp(TargetOpcode::G_XOR, cast<BinaryOperator>(Inst));
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// Branch operations.
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case Instruction::Br:
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return translateBr(cast<BranchInst>(Inst));
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case Instruction::Ret:
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return translateReturn(cast<ReturnInst>(Inst));
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// Calls
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case Instruction::Call:
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return translateCall(cast<CallInst>(Inst));
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// Casts and allied operations
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case Instruction::BitCast:
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return translateBitCast(cast<CastInst>(Inst));
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case Instruction::IntToPtr:
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return translateCast(TargetOpcode::G_INTTOPTR, cast<CastInst>(Inst));
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case Instruction::PtrToInt:
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return translateCast(TargetOpcode::G_PTRTOINT, cast<CastInst>(Inst));
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case Instruction::Trunc:
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return translateCast(TargetOpcode::G_TRUNC, cast<CastInst>(Inst));
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// Memory ops.
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case Instruction::Load:
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return translateLoad(cast<LoadInst>(Inst));
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case Instruction::Store:
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return translateStore(cast<StoreInst>(Inst));
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case Instruction::Alloca:
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return translateStaticAlloca(cast<AllocaInst>(Inst));
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case Instruction::PHI:
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return translatePhi(cast<PHINode>(Inst));
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case Instruction::Unreachable:
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return true;
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#define HANDLE_INST(NUM, OPCODE, CLASS) \
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case Instruction::OPCODE: return translate##OPCODE(Inst);
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#include "llvm/IR/Instruction.def"
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default:
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llvm_unreachable("Opcode not supported");
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llvm_unreachable("unknown opcode");
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}
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}
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@ -338,7 +296,15 @@ bool IRTranslator::translate(const Constant &C, unsigned Reg) {
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EntryBuilder.buildConstant(LLT{*CI->getType()}, Reg, CI->getZExtValue());
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else if (isa<UndefValue>(C))
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EntryBuilder.buildInstr(TargetOpcode::IMPLICIT_DEF).addDef(Reg);
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else
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else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
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switch(CE->getOpcode()) {
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#define HANDLE_INST(NUM, OPCODE, CLASS) \
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case Instruction::OPCODE: return translate##OPCODE(*CE);
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#include "llvm/IR/Instruction.def"
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default:
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llvm_unreachable("unknown opcode");
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}
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} else
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llvm_unreachable("unhandled constant kind");
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return true;
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@ -389,3 +389,11 @@ define i32 @constant_int_start() {
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define i32 @test_undef() {
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ret i32 undef
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}
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; CHECK-LABEL: name: test_constant_inttoptr
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; CHECK: [[ONE:%[0-9]+]](64) = G_CONSTANT s64 1
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; CHECK: [[PTR:%[0-9]+]](64) = G_INTTOPTR { p0, s64 } [[ONE]]
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; CHECK: %x0 = COPY [[PTR]]
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define i8* @test_constant_inttoptr() {
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ret i8* inttoptr(i64 1 to i8*)
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}
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