From 3531453371d80c16d21df7815e19d00c8c4f544f Mon Sep 17 00:00:00 2001
From: Diana Picus <diana.picus@linaro.org>
Date: Thu, 9 May 2019 09:49:36 +0000
Subject: [PATCH] [ARM GlobalISel] Map DBG_VALUE for types != s32

...and make sure we fail elegantly for unsupported values.

s64 goes into DPR, anything <= 32 into GPR.

llvm-svn: 360321
---
 llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp   | 10 +++-
 .../ARM/GlobalISel/arm-regbankselect.mir      | 46 +++++++++++++------
 2 files changed, 39 insertions(+), 17 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
index 021c13115e35..d03b482043ee 100644
--- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -433,8 +433,14 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     break;
   case DBG_VALUE: {
     SmallVector<const ValueMapping *, 4> OperandBanks(NumOperands);
-    if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg())
-      OperandBanks[0] = &ARM::ValueMappings[ARM::GPR3OpsIdx];
+    const MachineOperand &MaybeReg = MI.getOperand(0);
+    if (MaybeReg.isReg() && MaybeReg.getReg()) {
+      unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits();
+      if (Size > 32 && Size != 64)
+        return getInvalidInstructionMapping();
+      OperandBanks[0] = Size == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
+                                   : &ARM::ValueMappings[ARM::GPR3OpsIdx];
+    }
     OperandsMapping = getOperandsMapping(OperandBanks);
     break;
   }
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
index 6b24fda441a4..5aadc44f9579 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
@@ -1541,36 +1541,52 @@ registers:
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
 body:             |
   bb.0:
-    liveins: $r0, $s1
+    liveins: $r0, $s1, $d2
 
     %0(s32) = COPY $r0
-    %1(s32) = COPY $s1
 
-    ; {{%[0-9]+}}:gpr = G_ADD
-    %2(s32) = G_ADD %0, %0
+    ; CHECK: {{%[0-9]+}}:gprb(s32) = G_ADD
+    %1(s32) = G_ADD %0, %0
 
-    ; DBG_VALUE {{%[0-9]+}}:gpr, $noreg, !7, !DIExpression(), debug-location !9
-    DBG_VALUE %2(s32), $noreg, !7, !DIExpression(), debug-location !9
+    ; CHECK: DBG_VALUE {{%[0-9]+}}(s32), $noreg
+    DBG_VALUE %1(s32), $noreg, !7, !DIExpression(), debug-location !9
 
-    ; {{%[0-9]+}}:fpr = G_FADD
-    %3(s32) = G_FADD %1, %1
+    $r0 = COPY %1(s32)
 
-    ; DBG_VALUE {{%[0-9]+}}:fpr, $noreg, !7, !DIExpression(), debug-location !9
+    %2(s32) = COPY $s1
+
+    ; CHECK: {{%[0-9]+}}:fprb(s32) = G_FADD
+    %3(s32) = G_FADD %2, %2
+
+    ; CHECK: DBG_VALUE {{%[0-9]+}}(s32), $noreg
     DBG_VALUE %3(s32), $noreg, !7, !DIExpression(), debug-location !9
 
-    ; DBG_VALUE i32 42, 0, !7, !DIExpression(), debug-location !9
+    $s1 = COPY %3(s32)
+
+    %4(s64) = COPY $d2
+
+    ; CHECK: {{%[0-9]+}}:fprb(s64) = G_FADD
+    %5(s64) = G_FADD %4, %4
+
+    ; CHECK: DBG_VALUE {{%[0-9]+}}(s64), $noreg
+    DBG_VALUE %5(s64), $noreg, !7, !DIExpression(), debug-location !9
+
+    $d2 = COPY %5(s64)
+
+    ; CHECK: DBG_VALUE i32 42, 0
     DBG_VALUE i32 42, 0, !7, !DIExpression(), debug-location !9
 
-    ; DBG_VALUE float 1.000000e+00, 0, !7, !DIExpression(), debug-location !9
+    ; CHECK: DBG_VALUE float 1.000000e+00, 0
     DBG_VALUE float 1.000000e+00, 0, !7, !DIExpression(), debug-location !9
 
-    ; DBG_VALUE $noreg, 0, !7, !DIExpression(), debug-location !9
+    ; CHECK: DBG_VALUE $noreg, 0
     DBG_VALUE $noreg, 0, !7, !DIExpression(), debug-location !9
 
-    $r0 = COPY %2(s32)
-    $s1 = COPY %3(s32)
-    BX_RET 14, $noreg, implicit $r0, implicit $s1
+    $d2 = COPY %5(s64)
+    BX_RET 14, $noreg, implicit $r0, implicit $s1, implicit $d2
 
 ...