maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[ARM GlobalISel] Map DBG_VALUE for types != s32 

...and make sure we fail elegantly for unsupported values.

s64 goes into DPR, anything <= 32 into GPR.

llvm-svn: 360321
This commit is contained in:
Diana Picus 2019-05-09 09:49:36 +00:00
parent b1b09e5b55
commit 3531453371
2 changed files with 39 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
View File

@ -433,8 +433,14 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
break;
case DBG_VALUE: {
SmallVector<const ValueMapping *, 4> OperandBanks(NumOperands);
if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg())
OperandBanks[0] = &ARM::ValueMappings[ARM::GPR3OpsIdx];
const MachineOperand &MaybeReg = MI.getOperand(0);
if (MaybeReg.isReg() && MaybeReg.getReg()) {
unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits();
if (Size > 32 && Size != 64)
return getInvalidInstructionMapping();
OperandBanks[0] = Size == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
: &ARM::ValueMappings[ARM::GPR3OpsIdx];
}
OperandsMapping = getOperandsMapping(OperandBanks);
break;
}

46
llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
View File

@ -1541,36 +1541,52 @@ registers:
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0, $s1
liveins: $r0, $s1, $d2
%0(s32) = COPY $r0
%1(s32) = COPY $s1
; {{%[0-9]+}}:gpr = G_ADD
%2(s32) = G_ADD %0, %0
; CHECK: {{%[0-9]+}}:gprb(s32) = G_ADD
%1(s32) = G_ADD %0, %0
; DBG_VALUE {{%[0-9]+}}:gpr, $noreg, !7, !DIExpression(), debug-location !9
DBG_VALUE %2(s32), $noreg, !7, !DIExpression(), debug-location !9
; CHECK: DBG_VALUE {{%[0-9]+}}(s32), $noreg
DBG_VALUE %1(s32), $noreg, !7, !DIExpression(), debug-location !9
; {{%[0-9]+}}:fpr = G_FADD
%3(s32) = G_FADD %1, %1
$r0 = COPY %1(s32)
; DBG_VALUE {{%[0-9]+}}:fpr, $noreg, !7, !DIExpression(), debug-location !9
%2(s32) = COPY $s1
; CHECK: {{%[0-9]+}}:fprb(s32) = G_FADD
%3(s32) = G_FADD %2, %2
; CHECK: DBG_VALUE {{%[0-9]+}}(s32), $noreg
DBG_VALUE %3(s32), $noreg, !7, !DIExpression(), debug-location !9
; DBG_VALUE i32 42, 0, !7, !DIExpression(), debug-location !9
$s1 = COPY %3(s32)
%4(s64) = COPY $d2
; CHECK: {{%[0-9]+}}:fprb(s64) = G_FADD
%5(s64) = G_FADD %4, %4
; CHECK: DBG_VALUE {{%[0-9]+}}(s64), $noreg
DBG_VALUE %5(s64), $noreg, !7, !DIExpression(), debug-location !9
$d2 = COPY %5(s64)
; CHECK: DBG_VALUE i32 42, 0
DBG_VALUE i32 42, 0, !7, !DIExpression(), debug-location !9
; DBG_VALUE float 1.000000e+00, 0, !7, !DIExpression(), debug-location !9
; CHECK: DBG_VALUE float 1.000000e+00, 0
DBG_VALUE float 1.000000e+00, 0, !7, !DIExpression(), debug-location !9
; DBG_VALUE $noreg, 0, !7, !DIExpression(), debug-location !9
; CHECK: DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0, !7, !DIExpression(), debug-location !9
$r0 = COPY %2(s32)
$s1 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0, implicit $s1
$d2 = COPY %5(s64)
BX_RET 14, $noreg, implicit $r0, implicit $s1, implicit $d2
...