forked from OSchip/llvm-project
[RISCV][NFC] Add new test cases for mul
This commit is contained in:
Ben Shi
parent
ddb82fc76c
commit
351a45ca73
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@ -972,3 +972,207 @@ define i64 @muli64_m3840(i64 %a) nounwind {
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%1 = mul i64 %a, -3840
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ret i64 %1
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}
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define i128 @muli128_m3840(i128 %a) nounwind {
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; RV32I-LABEL: muli128_m3840:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -64
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; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: lw a2, 4(a1)
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; RV32I-NEXT: lw a4, 8(a1)
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; RV32I-NEXT: lw a1, 12(a1)
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; RV32I-NEXT: mv s0, a0
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; RV32I-NEXT: addi a0, zero, -1
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; RV32I-NEXT: sw a0, 20(sp)
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; RV32I-NEXT: sw a0, 16(sp)
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; RV32I-NEXT: sw a0, 12(sp)
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; RV32I-NEXT: lui a0, 1048575
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; RV32I-NEXT: addi a0, a0, 256
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; RV32I-NEXT: sw a0, 8(sp)
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; RV32I-NEXT: sw a1, 36(sp)
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; RV32I-NEXT: sw a4, 32(sp)
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; RV32I-NEXT: sw a2, 28(sp)
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; RV32I-NEXT: addi a0, sp, 40
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; RV32I-NEXT: addi a1, sp, 24
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; RV32I-NEXT: addi a2, sp, 8
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; RV32I-NEXT: sw a3, 24(sp)
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; RV32I-NEXT: call __multi3@plt
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; RV32I-NEXT: lw a0, 52(sp)
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; RV32I-NEXT: lw a1, 48(sp)
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; RV32I-NEXT: lw a2, 44(sp)
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; RV32I-NEXT: lw a3, 40(sp)
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; RV32I-NEXT: sw a0, 12(s0)
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; RV32I-NEXT: sw a1, 8(s0)
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; RV32I-NEXT: sw a2, 4(s0)
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; RV32I-NEXT: sw a3, 0(s0)
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; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 64
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: muli128_m3840:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi sp, sp, -64
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; RV32IM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
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; RV32IM-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
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; RV32IM-NEXT: lw a3, 0(a1)
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; RV32IM-NEXT: lw a2, 4(a1)
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; RV32IM-NEXT: lw a4, 8(a1)
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; RV32IM-NEXT: lw a1, 12(a1)
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; RV32IM-NEXT: mv s0, a0
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; RV32IM-NEXT: addi a0, zero, -1
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; RV32IM-NEXT: sw a0, 20(sp)
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; RV32IM-NEXT: sw a0, 16(sp)
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; RV32IM-NEXT: sw a0, 12(sp)
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; RV32IM-NEXT: lui a0, 1048575
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; RV32IM-NEXT: addi a0, a0, 256
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; RV32IM-NEXT: sw a0, 8(sp)
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; RV32IM-NEXT: sw a1, 36(sp)
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; RV32IM-NEXT: sw a4, 32(sp)
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; RV32IM-NEXT: sw a2, 28(sp)
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; RV32IM-NEXT: addi a0, sp, 40
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; RV32IM-NEXT: addi a1, sp, 24
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; RV32IM-NEXT: addi a2, sp, 8
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; RV32IM-NEXT: sw a3, 24(sp)
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; RV32IM-NEXT: call __multi3@plt
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; RV32IM-NEXT: lw a0, 52(sp)
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; RV32IM-NEXT: lw a1, 48(sp)
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; RV32IM-NEXT: lw a2, 44(sp)
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; RV32IM-NEXT: lw a3, 40(sp)
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; RV32IM-NEXT: sw a0, 12(s0)
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; RV32IM-NEXT: sw a1, 8(s0)
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; RV32IM-NEXT: sw a2, 4(s0)
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; RV32IM-NEXT: sw a3, 0(s0)
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; RV32IM-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
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; RV32IM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
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; RV32IM-NEXT: addi sp, sp, 64
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: muli128_m3840:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: lui a2, 1048575
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; RV64I-NEXT: addiw a2, a2, 256
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; RV64I-NEXT: addi a3, zero, -1
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; RV64I-NEXT: call __multi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: muli128_m3840:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: lui a2, 1048575
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; RV64IM-NEXT: addiw a2, a2, 256
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; RV64IM-NEXT: mul a1, a1, a2
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; RV64IM-NEXT: mulhu a3, a0, a2
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; RV64IM-NEXT: sub a3, a3, a0
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; RV64IM-NEXT: add a1, a3, a1
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; RV64IM-NEXT: mul a0, a0, a2
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; RV64IM-NEXT: ret
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%1 = mul i128 %a, -3840
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ret i128 %1
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}
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define i128 @muli128_m63(i128 %a) nounwind {
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; RV32I-LABEL: muli128_m63:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -64
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; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: lw a2, 4(a1)
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; RV32I-NEXT: lw a4, 8(a1)
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; RV32I-NEXT: lw a1, 12(a1)
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; RV32I-NEXT: mv s0, a0
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; RV32I-NEXT: addi a0, zero, -1
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; RV32I-NEXT: sw a0, 20(sp)
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; RV32I-NEXT: sw a0, 16(sp)
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; RV32I-NEXT: sw a0, 12(sp)
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; RV32I-NEXT: addi a0, zero, -63
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; RV32I-NEXT: sw a0, 8(sp)
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; RV32I-NEXT: sw a1, 36(sp)
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; RV32I-NEXT: sw a4, 32(sp)
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; RV32I-NEXT: sw a2, 28(sp)
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; RV32I-NEXT: addi a0, sp, 40
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; RV32I-NEXT: addi a1, sp, 24
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; RV32I-NEXT: addi a2, sp, 8
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; RV32I-NEXT: sw a3, 24(sp)
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; RV32I-NEXT: call __multi3@plt
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; RV32I-NEXT: lw a0, 52(sp)
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; RV32I-NEXT: lw a1, 48(sp)
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; RV32I-NEXT: lw a2, 44(sp)
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; RV32I-NEXT: lw a3, 40(sp)
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; RV32I-NEXT: sw a0, 12(s0)
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; RV32I-NEXT: sw a1, 8(s0)
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; RV32I-NEXT: sw a2, 4(s0)
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; RV32I-NEXT: sw a3, 0(s0)
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; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 64
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: muli128_m63:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi sp, sp, -64
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; RV32IM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
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; RV32IM-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
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; RV32IM-NEXT: lw a3, 0(a1)
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; RV32IM-NEXT: lw a2, 4(a1)
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; RV32IM-NEXT: lw a4, 8(a1)
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; RV32IM-NEXT: lw a1, 12(a1)
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; RV32IM-NEXT: mv s0, a0
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; RV32IM-NEXT: addi a0, zero, -1
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; RV32IM-NEXT: sw a0, 20(sp)
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; RV32IM-NEXT: sw a0, 16(sp)
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; RV32IM-NEXT: sw a0, 12(sp)
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; RV32IM-NEXT: addi a0, zero, -63
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; RV32IM-NEXT: sw a0, 8(sp)
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; RV32IM-NEXT: sw a1, 36(sp)
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; RV32IM-NEXT: sw a4, 32(sp)
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; RV32IM-NEXT: sw a2, 28(sp)
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; RV32IM-NEXT: addi a0, sp, 40
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; RV32IM-NEXT: addi a1, sp, 24
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; RV32IM-NEXT: addi a2, sp, 8
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; RV32IM-NEXT: sw a3, 24(sp)
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; RV32IM-NEXT: call __multi3@plt
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; RV32IM-NEXT: lw a0, 52(sp)
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; RV32IM-NEXT: lw a1, 48(sp)
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; RV32IM-NEXT: lw a2, 44(sp)
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; RV32IM-NEXT: lw a3, 40(sp)
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; RV32IM-NEXT: sw a0, 12(s0)
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; RV32IM-NEXT: sw a1, 8(s0)
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; RV32IM-NEXT: sw a2, 4(s0)
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; RV32IM-NEXT: sw a3, 0(s0)
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; RV32IM-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
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; RV32IM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
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; RV32IM-NEXT: addi sp, sp, 64
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: muli128_m63:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: addi a2, zero, -63
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; RV64I-NEXT: addi a3, zero, -1
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; RV64I-NEXT: call __multi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: muli128_m63:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: slli a2, a1, 6
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; RV64IM-NEXT: sub a1, a1, a2
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; RV64IM-NEXT: addi a2, zero, -63
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; RV64IM-NEXT: mulhu a2, a0, a2
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; RV64IM-NEXT: sub a2, a2, a0
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; RV64IM-NEXT: add a1, a2, a1
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; RV64IM-NEXT: slli a2, a0, 6
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; RV64IM-NEXT: sub a0, a0, a2
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; RV64IM-NEXT: ret
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%1 = mul i128 %a, -63
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ret i128 %1
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}
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