From 350ff2c084470a846bd652d5d4fc99413f65bfa4 Mon Sep 17 00:00:00 2001
From: Andrew Trick <atrick@apple.com>
Date: Tue, 21 Jan 2014 21:27:37 +0000
Subject: [PATCH] Fix PR18572 - llc crash during
 GenericScheduler::initPolicy().

Generalized the heuristic that looks at the (very rough) size of the
register file before enabling regpressure tracking.

llvm-svn: 199766
---
 llvm/lib/CodeGen/MachineScheduler.cpp    | 14 ++++++++++----
 llvm/test/CodeGen/Mips/misched-msp430.ll | 20 ++++++++++++++++++++
 2 files changed, 30 insertions(+), 4 deletions(-)
 create mode 100644 llvm/test/CodeGen/Mips/misched-msp430.ll

diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index b1dd34bcb7dd..4812b30526aa 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -2531,10 +2531,16 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
   // Avoid setting up the register pressure tracker for small regions to save
   // compile time. As a rough heuristic, only track pressure when the number of
   // schedulable instructions exceeds half the integer register file.
-  unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
-    TM.getTargetLowering()->getRegClassFor(MVT::i32));
-
-  RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
+  RegionPolicy.ShouldTrackPressure = true;
+  unsigned LegalIntVT = MVT::i32;
+  for (; LegalIntVT > (unsigned)MVT::i1; --LegalIntVT) {
+    if (TM.getTargetLowering()->isTypeLegal((MVT::SimpleValueType)LegalIntVT)) {
+      unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
+        TM.getTargetLowering()->getRegClassFor(
+          (MVT::SimpleValueType)LegalIntVT));
+      RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
+    }
+  }
 
   // For generic targets, we default to bottom-up, because it's simpler and more
   // compile-time optimizations have been implemented in that direction.
diff --git a/llvm/test/CodeGen/Mips/misched-msp430.ll b/llvm/test/CodeGen/Mips/misched-msp430.ll
new file mode 100644
index 000000000000..24ca47b2e04f
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/misched-msp430.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple=msp430-unknown-unknown -enable-misched | FileCheck %s
+
+target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
+
+@y = common global i16 0, align 2
+@x = common global i16 0, align 2
+
+; Test that the MI Scheduler's initPolicy does not crash when i32 is
+; unsupported. The content of the asm check below is unimportant. It
+; only verifies that the code generator ran succesfully.
+;
+; CHECK-LABEL: @f
+; CHECK: mov.w &y, &x
+; CHECK: ret
+define void @f() {
+entry:
+  %0 = load i16* @y, align 2
+  store i16 %0, i16* @x, align 2
+  ret void
+}