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Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes. 

llvm-svn: 55623
This commit is contained in:
Evan Cheng 2008-09-02 06:51:36 +00:00
parent ee29c9c2fc
commit 34f3a962b0
3 changed files with 17 additions and 13 deletions
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14
llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp
View File

@ -33,7 +33,8 @@ namespace {
/// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
///
int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
unsigned getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO);
public:
static char ID;
@ -55,7 +56,7 @@ namespace {
/// CodeEmitterGenerator using TableGen, produces the binary encoding for
/// machine instructions.
///
unsigned getBinaryCodeForInstr(MachineInstr &MI);
unsigned getBinaryCodeForInstr(const MachineInstr &MI);
private:
void emitBasicBlock(MachineBasicBlock &MBB);
@ -87,7 +88,7 @@ void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
MCE.StartMachineBasicBlock(&MBB);
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
I != E; ++I) {
MachineInstr &MI = *I;
const MachineInstr &MI = *I;
switch(MI.getOpcode()) {
default:
MCE.emitWordLE(getBinaryCodeForInstr(*I));
@ -141,10 +142,11 @@ static unsigned getAlphaRegNumber(unsigned Reg) {
}
}
int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) {
int rv = 0; // Return value; defaults to 0 for unhandled cases
// or things that get fixed up later by the JIT.
unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
// or things that get fixed up later by the JIT.
if (MO.isRegister()) {
rv = getAlphaRegNumber(MO.getReg());

13
llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
View File

@ -38,7 +38,7 @@ namespace {
/// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
///
int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
unsigned getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO);
void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<MachineModuleInfo>();
@ -68,7 +68,7 @@ namespace {
/// CodeEmitterGenerator using TableGen, produces the binary encoding for
/// machine instructions.
///
unsigned getBinaryCodeForInstr(MachineInstr &MI);
unsigned getBinaryCodeForInstr(const MachineInstr &MI);
};
char PPCCodeEmitter::ID = 0;
}
@ -100,10 +100,10 @@ void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
MCE.StartMachineBasicBlock(&MBB);
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
MachineInstr &MI = *I;
const MachineInstr &MI = *I;
switch (MI.getOpcode()) {
default:
MCE.emitWordBE(getBinaryCodeForInstr(*I));
MCE.emitWordBE(getBinaryCodeForInstr(MI));
break;
case TargetInstrInfo::DBG_LABEL:
case TargetInstrInfo::EH_LABEL:
@ -121,9 +121,10 @@ void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
}
}
int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) {
intptr_t rv = 0; // Return value; defaults to 0 for unhandled cases
unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
// or things that get fixed up later by the JIT.
if (MO.isRegister()) {
rv = PPCRegisterInfo::getRegisterNumbering(MO.getReg());

3
llvm/utils/TableGen/CodeEmitterGen.cpp
View File

@ -89,7 +89,7 @@ void CodeEmitterGen::run(std::ostream &o) {
// Emit function declaration
o << "unsigned " << Target.getName() << "CodeEmitter::"
<< "getBinaryCodeForInstr(MachineInstr &MI) {\n";
<< "getBinaryCodeForInstr(const MachineInstr &MI) {\n";
// Emit instruction base values
o << " static const unsigned InstBits[] = {\n";
@ -221,6 +221,7 @@ void CodeEmitterGen::run(std::ostream &o) {
o << " const unsigned opcode = MI.getOpcode();\n"
<< " unsigned Value = InstBits[opcode];\n"
<< " unsigned op;\n"
<< " op = op; // suppress warning\n"
<< " switch (opcode) {\n";
// Emit each case statement