forked from OSchip/llvm-project
Add operand info for F3_[12] instructions, getting V8 back to basic functionality.
With this, Regression/CodeGen/SparcV8/basictest.ll now passes. Lets hear it for regression tests :) llvm-svn: 24738
This commit is contained in:
Chris Lattner
parent
0d129ae8b1
commit
34e80f0114
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@ -58,10 +58,12 @@ class F3 : InstV8 {
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// Specific F3 classes: SparcV8 manual, page 44
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//
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class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3 {
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class F3_1<bits<2> opVal, bits<6> op3val, dag ops, string name> : F3 {
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bits<8> asi = 0; // asi not currently used in SparcV8
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bits<5> rs2;
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dag OperandList = ops;
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let op = opVal;
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let op3 = op3val;
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let Name = name;
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@ -71,9 +73,11 @@ class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3 {
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let Inst{4-0} = rs2;
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}
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class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3 {
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class F3_2<bits<2> opVal, bits<6> op3val, dag ops, string name> : F3 {
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bits<13> simm13;
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dag OperandList = ops;
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let op = opVal;
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let op3 = op3val;
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let Name = name;
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@ -50,47 +50,74 @@ def FpMOVD : PseudoInstV8<"FpMOVD", (ops)>; // pseudo 64-bit double move
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// special cases of JMPL:
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let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
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let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
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def RET : F3_2<2, 0b111000, "ret">;
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def RET : F3_2<2, 0b111000,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ret">;
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let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
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def RETL: F3_2<2, 0b111000, "retl">;
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def RETL: F3_2<2, 0b111000,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "retl">;
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}
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// CMP is a special case of SUBCC where destination is ignored, by setting it to
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// %g0 (hardwired zero).
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// FIXME: should keep track of the fact that it defs the integer condition codes
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let rd = 0 in
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def CMPri: F3_2<2, 0b010100, "cmp">;
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def CMPri: F3_2<2, 0b010100,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "cmp">;
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// Section B.1 - Load Integer Instructions, p. 90
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def LDSB: F3_2<3, 0b001001, "ldsb">;
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def LDSH: F3_2<3, 0b001010, "ldsh">;
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def LDUB: F3_2<3, 0b000001, "ldub">;
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def LDUH: F3_2<3, 0b000010, "lduh">;
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def LD : F3_2<3, 0b000000, "ld">;
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def LDD : F3_2<3, 0b000011, "ldd">;
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def LDSB: F3_2<3, 0b001001,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldsb">;
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def LDSH: F3_2<3, 0b001010,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldsh">;
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def LDUB: F3_2<3, 0b000001,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldub">;
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def LDUH: F3_2<3, 0b000010,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "lduh">;
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def LD : F3_2<3, 0b000000,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ld">;
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def LDD : F3_2<3, 0b000011,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldd">;
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// Section B.2 - Load Floating-point Instructions, p. 92
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def LDFrr : F3_1<3, 0b100000, "ld">;
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def LDFri : F3_2<3, 0b100000, "ld">;
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def LDDFrr : F3_1<3, 0b100011, "ldd">;
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def LDDFri : F3_2<3, 0b100011, "ldd">;
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def LDFSRrr: F3_1<3, 0b100001, "ld">;
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def LDFSRri: F3_2<3, 0b100001, "ld">;
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def LDFrr : F3_1<3, 0b100000,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "ld">;
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def LDFri : F3_2<3, 0b100000,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ld">;
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def LDDFrr : F3_1<3, 0b100011,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "ldd">;
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def LDDFri : F3_2<3, 0b100011,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldd">;
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def LDFSRrr: F3_1<3, 0b100001,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "ld">;
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def LDFSRri: F3_2<3, 0b100001,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ld">;
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// Section B.4 - Store Integer Instructions, p. 95
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def STB : F3_2<3, 0b000101, "stb">;
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def STH : F3_2<3, 0b000110, "sth">;
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def ST : F3_2<3, 0b000100, "st">;
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def STD : F3_2<3, 0b000111, "std">;
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def STB : F3_2<3, 0b000101,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "stb">;
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def STH : F3_2<3, 0b000110,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sth">;
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def ST : F3_2<3, 0b000100,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "st">;
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def STD : F3_2<3, 0b000111,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "std">;
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// Section B.5 - Store Floating-point Instructions, p. 97
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def STFrr : F3_1<3, 0b100100, "st">;
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def STFri : F3_2<3, 0b100100, "st">;
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def STDFrr : F3_1<3, 0b100111, "std">;
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def STDFri : F3_2<3, 0b100111, "std">;
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def STFSRrr : F3_1<3, 0b100101, "st">;
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def STFSRri : F3_2<3, 0b100101, "st">;
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def STDFQrr : F3_1<3, 0b100110, "std">;
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def STDFQri : F3_2<3, 0b100110, "std">;
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def STFrr : F3_1<3, 0b100100,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "st">;
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def STFri : F3_2<3, 0b100100,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "st">;
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def STDFrr : F3_1<3, 0b100111,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "std">;
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def STDFri : F3_2<3, 0b100111,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "std">;
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def STFSRrr : F3_1<3, 0b100101,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "st">;
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def STFSRri : F3_2<3, 0b100101,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "st">;
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def STDFQrr : F3_1<3, 0b100110,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "std">;
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def STDFQri : F3_2<3, 0b100110,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "std">;
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100, "sethi">;
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@ -101,84 +128,150 @@ let rd = 0, imm22 = 0 in
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def NOP : F2_1<0b100, "nop">;
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// Section B.11 - Logical Instructions, p. 106
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def ANDrr : F3_1<2, 0b000001, "and">;
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def ANDri : F3_2<2, 0b000001, "and">;
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def ANDCCrr : F3_1<2, 0b010001, "andcc">;
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def ANDCCri : F3_2<2, 0b010001, "andcc">;
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def ANDNrr : F3_1<2, 0b000101, "andn">;
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def ANDNri : F3_2<2, 0b000101, "andn">;
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def ANDNCCrr: F3_1<2, 0b010101, "andncc">;
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def ANDNCCri: F3_2<2, 0b010101, "andncc">;
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def ORrr : F3_1<2, 0b000010, "or">;
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def ORri : F3_2<2, 0b000010, "or">;
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def ORCCrr : F3_1<2, 0b010010, "orcc">;
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def ORCCri : F3_2<2, 0b010010, "orcc">;
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def ORNrr : F3_1<2, 0b000110, "orn">;
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def ORNri : F3_2<2, 0b000110, "orn">;
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def ORNCCrr : F3_1<2, 0b010110, "orncc">;
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def ORNCCri : F3_2<2, 0b010110, "orncc">;
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def XORrr : F3_1<2, 0b000011, "xor">;
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def XORri : F3_2<2, 0b000011, "xor">;
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def XORCCrr : F3_1<2, 0b010011, "xorcc">;
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def XORCCri : F3_2<2, 0b010011, "xorcc">;
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def XNORrr : F3_1<2, 0b000111, "xnor">;
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def XNORri : F3_2<2, 0b000111, "xnor">;
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def XNORCCrr: F3_1<2, 0b010111, "xnorcc">;
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def XNORCCri: F3_2<2, 0b010111, "xnorcc">;
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def ANDrr : F3_1<2, 0b000001,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "and">;
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def ANDri : F3_2<2, 0b000001,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "and">;
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def ANDCCrr : F3_1<2, 0b010001,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "andcc">;
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def ANDCCri : F3_2<2, 0b010001,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "andcc">;
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def ANDNrr : F3_1<2, 0b000101,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "andn">;
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def ANDNri : F3_2<2, 0b000101,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "andn">;
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def ANDNCCrr: F3_1<2, 0b010101,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "andncc">;
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def ANDNCCri: F3_2<2, 0b010101,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "andncc">;
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def ORrr : F3_1<2, 0b000010,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "or">;
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def ORri : F3_2<2, 0b000010,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "or">;
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def ORCCrr : F3_1<2, 0b010010,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "orcc">;
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def ORCCri : F3_2<2, 0b010010,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "orcc">;
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def ORNrr : F3_1<2, 0b000110,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "orn">;
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def ORNri : F3_2<2, 0b000110,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "orn">;
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def ORNCCrr : F3_1<2, 0b010110,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "orncc">;
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def ORNCCri : F3_2<2, 0b010110,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "orncc">;
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def XORrr : F3_1<2, 0b000011,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "xor">;
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def XORri : F3_2<2, 0b000011,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "xor">;
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def XORCCrr : F3_1<2, 0b010011,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "xorcc">;
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def XORCCri : F3_2<2, 0b010011,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "xorcc">;
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def XNORrr : F3_1<2, 0b000111,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "xnor">;
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def XNORri : F3_2<2, 0b000111,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "xnor">;
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def XNORCCrr: F3_1<2, 0b010111,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "xnorcc">;
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def XNORCCri: F3_2<2, 0b010111,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "xnorcc">;
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// Section B.12 - Shift Instructions, p. 107
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def SLLrr : F3_1<2, 0b100101, "sll">;
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def SLLri : F3_2<2, 0b100101, "sll">;
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def SRLrr : F3_1<2, 0b100110, "srl">;
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def SRLri : F3_2<2, 0b100110, "srl">;
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def SRArr : F3_1<2, 0b100111, "sra">;
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def SRAri : F3_2<2, 0b100111, "sra">;
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def SLLrr : F3_1<2, 0b100101,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sll">;
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def SLLri : F3_2<2, 0b100101,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sll">;
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def SRLrr : F3_1<2, 0b100110,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "srl">;
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def SRLri : F3_2<2, 0b100110,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "srl">;
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def SRArr : F3_1<2, 0b100111,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sra">;
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def SRAri : F3_2<2, 0b100111,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sra">;
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// Section B.13 - Add Instructions, p. 108
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def ADDrr : F3_1<2, 0b000000, "add">;
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def ADDri : F3_2<2, 0b000000, "add">;
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def ADDCCrr : F3_1<2, 0b010000, "addcc">;
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def ADDCCri : F3_2<2, 0b010000, "addcc">;
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def ADDXrr : F3_1<2, 0b001000, "addx">;
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def ADDXri : F3_2<2, 0b001000, "addx">;
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def ADDXCCrr: F3_1<2, 0b011000, "addxcc">;
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def ADDXCCri: F3_2<2, 0b011000, "addxcc">;
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def ADDrr : F3_1<2, 0b000000,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "add">;
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def ADDri : F3_2<2, 0b000000,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "add">;
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def ADDCCrr : F3_1<2, 0b010000,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "addcc">;
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def ADDCCri : F3_2<2, 0b010000,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "addcc">;
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def ADDXrr : F3_1<2, 0b001000,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "addx">;
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def ADDXri : F3_2<2, 0b001000,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "addx">;
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def ADDXCCrr: F3_1<2, 0b011000,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "addxcc">;
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def ADDXCCri: F3_2<2, 0b011000,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "addxcc">;
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// Section B.15 - Subtract Instructions, p. 110
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def SUBrr : F3_1<2, 0b000100, "sub">;
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def SUBri : F3_2<2, 0b000100, "sub">;
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def SUBCCrr : F3_1<2, 0b010100, "subcc">;
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def SUBCCri : F3_2<2, 0b010100, "subcc">;
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def SUBXrr : F3_1<2, 0b001100, "subx">;
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def SUBXri : F3_2<2, 0b001100, "subx">;
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def SUBXCCrr: F3_1<2, 0b011100, "subxcc">;
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def SUBXCCri: F3_2<2, 0b011100, "subxcc">;
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def SUBrr : F3_1<2, 0b000100,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sub">;
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def SUBri : F3_2<2, 0b000100,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sub">;
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def SUBCCrr : F3_1<2, 0b010100,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "subcc">;
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def SUBCCri : F3_2<2, 0b010100,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "subcc">;
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def SUBXrr : F3_1<2, 0b001100,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "subx">;
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def SUBXri : F3_2<2, 0b001100,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "subx">;
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def SUBXCCrr: F3_1<2, 0b011100,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "subxcc">;
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def SUBXCCri: F3_2<2, 0b011100,
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(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "subxcc">;
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// Section B.18 - Multiply Instructions, p. 113
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def UMULrr : F3_1<2, 0b001010, "umul">;
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def UMULri : F3_2<2, 0b001010, "umul">;
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def SMULrr : F3_1<2, 0b001011, "smul">;
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def SMULri : F3_2<2, 0b001011, "smul">;
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def UMULCCrr: F3_1<2, 0b011010, "umulcc">;
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def UMULCCri: F3_2<2, 0b011010, "umulcc">;
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def SMULCCrr: F3_1<2, 0b011011, "smulcc">;
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def SMULCCri: F3_2<2, 0b011011, "smulcc">;
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def UMULrr : F3_1<2, 0b001010,
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(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "umul">;
|
||||
def UMULri : F3_2<2, 0b001010,
|
||||
(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "umul">;
|
||||
def SMULrr : F3_1<2, 0b001011,
|
||||
(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "smul">;
|
||||
def SMULri : F3_2<2, 0b001011,
|
||||
(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "smul">;
|
||||
def UMULCCrr: F3_1<2, 0b011010,
|
||||
(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "umulcc">;
|
||||
def UMULCCri: F3_2<2, 0b011010,
|
||||
(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "umulcc">;
|
||||
def SMULCCrr: F3_1<2, 0b011011,
|
||||
(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "smulcc">;
|
||||
def SMULCCri: F3_2<2, 0b011011,
|
||||
(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "smulcc">;
|
||||
|
||||
// Section B.19 - Divide Instructions, p. 115
|
||||
def UDIVrr : F3_1<2, 0b001110, "udiv">;
|
||||
def UDIVri : F3_2<2, 0b001110, "udiv">;
|
||||
def SDIVrr : F3_1<2, 0b001111, "sdiv">;
|
||||
def SDIVri : F3_2<2, 0b001111, "sdiv">;
|
||||
def UDIVCCrr : F3_1<2, 0b011110, "udivcc">;
|
||||
def UDIVCCri : F3_2<2, 0b011110, "udivcc">;
|
||||
def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">;
|
||||
def SDIVCCri : F3_2<2, 0b011111, "sdivcc">;
|
||||
def UDIVrr : F3_1<2, 0b001110,
|
||||
(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "udiv">;
|
||||
def UDIVri : F3_2<2, 0b001110,
|
||||
(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "udiv">;
|
||||
def SDIVrr : F3_1<2, 0b001111,
|
||||
(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sdiv">;
|
||||
def SDIVri : F3_2<2, 0b001111,
|
||||
(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sdiv">;
|
||||
def UDIVCCrr : F3_1<2, 0b011110,
|
||||
(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "udivcc">;
|
||||
def UDIVCCri : F3_2<2, 0b011110,
|
||||
(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "udivcc">;
|
||||
def SDIVCCrr : F3_1<2, 0b011111,
|
||||
(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sdivcc">;
|
||||
def SDIVCCri : F3_2<2, 0b011111,
|
||||
(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sdivcc">;
|
||||
|
||||
// Section B.20 - SAVE and RESTORE, p. 117
|
||||
def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
|
||||
def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r
|
||||
def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r
|
||||
def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r
|
||||
def SAVErr : F3_1<2, 0b111100,
|
||||
(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "save">;
|
||||
def SAVEri : F3_2<2, 0b111100,
|
||||
(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "save">;
|
||||
def RESTORErr : F3_1<2, 0b111101,
|
||||
(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "restore">;
|
||||
def RESTOREri : F3_2<2, 0b111101,
|
||||
(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "restore">;
|
||||
|
||||
// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
|
||||
|
||||
|
|
@ -248,12 +341,15 @@ let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
|
|||
// be an implicit def):
|
||||
let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
|
||||
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
|
||||
def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
|
||||
def JMPLrr : F3_1<2, 0b111000, (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "jmpl">;
|
||||
// jmpl [rs1+rs2], rd
|
||||
}
|
||||
|
||||
// Section B.29 - Write State Register Instructions
|
||||
def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd
|
||||
def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd
|
||||
def WRrr : F3_1<2, 0b110000,
|
||||
(ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "wr">;
|
||||
def WRri : F3_2<2, 0b110000,
|
||||
(ops IntRegs:$a, IntRegs:$b, i32imm:$c), "wr">; // wr rs1, imm, rd
|
||||
|
||||
// Convert Integer to Floating-point Instructions, p. 141
|
||||
def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">;
|
||||
|
|
|
|||
Loading…
Reference in New Issue