From 34db3c3a1847e549c40bceb32c1bca8093eb3a8c Mon Sep 17 00:00:00 2001
From: Thomas Lively <tlively@google.com>
Date: Wed, 18 Mar 2020 18:15:02 -0700
Subject: [PATCH] [WebAssembly] SIMD integer abs instructions

Summary:
These were merged to the SIMD proposal in
https://github.com/WebAssembly/simd/pull/128.

Depends on D76397 to avoid merge conflicts.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76399
---
 .../WebAssembly/WebAssemblyISelLowering.cpp   |  4 +++
 .../WebAssembly/WebAssemblyInstrSIMD.td       |  5 +++
 llvm/test/CodeGen/WebAssembly/simd-arith.ll   | 36 +++++++++++++++++++
 llvm/test/MC/WebAssembly/simd-encodings.s     |  9 +++++
 4 files changed, 54 insertions(+)

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 68e9aa644f24..a0c0af265095 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -125,6 +125,10 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
       for (auto T : {MVT::v16i8, MVT::v8i16})
         setOperationAction(Op, T, Legal);
 
+    // Support integer abs
+    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
+      setOperationAction(ISD::ABS, T, Legal);
+
     // Custom lower BUILD_VECTORs to minimize number of replace_lanes
     for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
                    MVT::v2f64})
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 7743a284091e..a9cb9177f5a2 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -575,6 +575,11 @@ multiclass SIMDReduce<SDNode op, string name, bits<32> baseInst> {
 // Integer vector negation
 def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
 
+// Integer absolute value: abs
+defm ABS : SIMDUnary<v16i8, "i8x16", abs, "abs", 225>;
+defm ABS : SIMDUnary<v8i16, "i16x8", abs, "abs", 226>;
+defm ABS : SIMDUnary<v4i32, "i32x4", abs, "abs", 227>;
+
 // Integer negation: neg
 defm NEG : SIMDUnaryInt<ivneg, "neg", 81>;
 
diff --git a/llvm/test/CodeGen/WebAssembly/simd-arith.ll b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
index 4ccc6f8b613f..78aabaf0272f 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-arith.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
@@ -118,6 +118,18 @@ define <16 x i8> @avgr_u_v16i8_wrap(<16 x i8> %x, <16 x i8> %y) {
   ret <16 x i8> %c
 }
 
+; CHECK-LABEL: abs_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .functype abs_v16i8 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i8x16.abs $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @abs_v16i8(<16 x i8> %x) {
+  %a = sub <16 x i8> zeroinitializer, %x
+  %b = icmp slt <16 x i8> %x, zeroinitializer
+  %c = select <16 x i1> %b, <16 x i8> %a, <16 x i8> %x
+  ret <16 x i8> %c
+}
+
 ; CHECK-LABEL: neg_v16i8:
 ; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype neg_v16i8 (v128) -> (v128){{$}}
@@ -431,6 +443,18 @@ define <8 x i16> @avgr_u_v8i16_wrap(<8 x i16> %x, <8 x i16> %y) {
   ret <8 x i16> %c
 }
 
+; CHECK-LABEL: abs_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .functype abs_v8i16 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.abs $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @abs_v8i16(<8 x i16> %x) {
+  %a = sub <8 x i16> zeroinitializer, %x
+  %b = icmp slt <8 x i16> %x, zeroinitializer
+  %c = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %x
+  ret <8 x i16> %c
+}
+
 ; CHECK-LABEL: neg_v8i16:
 ; NO-SIMD128-NOT: i16x8
 ; SIMD128-NEXT: .functype neg_v8i16 (v128) -> (v128){{$}}
@@ -713,6 +737,18 @@ define <4 x i32> @max_u_v4i32(<4 x i32> %x, <4 x i32> %y) {
   ret <4 x i32> %a
 }
 
+; CHECK-LABEL: abs_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .functype abs_v4i32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.abs $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @abs_v4i32(<4 x i32> %x) {
+  %a = sub <4 x i32> zeroinitializer, %x
+  %b = icmp slt <4 x i32> %x, zeroinitializer
+  %c = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %x
+  ret <4 x i32> %c
+}
+
 ; CHECK-LABEL: neg_v4i32:
 ; NO-SIMD128-NOT: i32x4
 ; SIMD128-NEXT: .functype neg_v4i32 (v128) -> (v128){{$}}
diff --git a/llvm/test/MC/WebAssembly/simd-encodings.s b/llvm/test/MC/WebAssembly/simd-encodings.s
index 68797cd114ec..023660ea4dca 100644
--- a/llvm/test/MC/WebAssembly/simd-encodings.s
+++ b/llvm/test/MC/WebAssembly/simd-encodings.s
@@ -580,6 +580,15 @@ main:
     # CHECK: i32x4.dot_i16x8_s # encoding: [0xfd,0xdb,0x01]
     i32x4.dot_i16x8_s
 
+    # CHECK: i8x16.abs # encoding: [0xfd,0xe1,0x01]
+    i8x16.abs
+
+    # CHECK: i16x8.abs # encoding: [0xfd,0xe2,0x01]
+    i16x8.abs
+
+    # CHECK: i32x4.abs # encoding: [0xfd,0xe3,0x01]
+    i32x4.abs
+
     # CHECK: i8x16.bitmask # encoding: [0xfd,0xe4,0x01]
     i8x16.bitmask