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[WebAssembly] SIMD integer abs instructions 

Summary:
These were merged to the SIMD proposal in
https://github.com/WebAssembly/simd/pull/128.

Depends on D76397 to avoid merge conflicts.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76399
This commit is contained in:
Thomas Lively 2020-03-18 18:15:02 -07:00
parent 6343526d64
commit 34db3c3a18
4 changed files with 54 additions and 0 deletions
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4
llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
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@ -125,6 +125,10 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
for (auto T : {MVT::v16i8, MVT::v8i16})
setOperationAction(Op, T, Legal);
// Support integer abs
for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
setOperationAction(ISD::ABS, T, Legal);
// Custom lower BUILD_VECTORs to minimize number of replace_lanes
for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
MVT::v2f64})

5
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
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@ -575,6 +575,11 @@ multiclass SIMDReduce<SDNode op, string name, bits<32> baseInst> {
// Integer vector negation
def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
// Integer absolute value: abs
defm ABS : SIMDUnary<v16i8, "i8x16", abs, "abs", 225>;
defm ABS : SIMDUnary<v8i16, "i16x8", abs, "abs", 226>;
defm ABS : SIMDUnary<v4i32, "i32x4", abs, "abs", 227>;
// Integer negation: neg
defm NEG : SIMDUnaryInt<ivneg, "neg", 81>;

36
llvm/test/CodeGen/WebAssembly/simd-arith.ll
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@ -118,6 +118,18 @@ define <16 x i8> @avgr_u_v16i8_wrap(<16 x i8> %x, <16 x i8> %y) {
ret <16 x i8> %c
}
; CHECK-LABEL: abs_v16i8:
; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype abs_v16i8 (v128) -> (v128){{$}}
; SIMD128-NEXT: i8x16.abs $push[[R:[0-9]+]]=, $0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <16 x i8> @abs_v16i8(<16 x i8> %x) {
%a = sub <16 x i8> zeroinitializer, %x
%b = icmp slt <16 x i8> %x, zeroinitializer
%c = select <16 x i1> %b, <16 x i8> %a, <16 x i8> %x
ret <16 x i8> %c
}
; CHECK-LABEL: neg_v16i8:
; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype neg_v16i8 (v128) -> (v128){{$}}
@ -431,6 +443,18 @@ define <8 x i16> @avgr_u_v8i16_wrap(<8 x i16> %x, <8 x i16> %y) {
ret <8 x i16> %c
}
; CHECK-LABEL: abs_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .functype abs_v8i16 (v128) -> (v128){{$}}
; SIMD128-NEXT: i16x8.abs $push[[R:[0-9]+]]=, $0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <8 x i16> @abs_v8i16(<8 x i16> %x) {
%a = sub <8 x i16> zeroinitializer, %x
%b = icmp slt <8 x i16> %x, zeroinitializer
%c = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %x
ret <8 x i16> %c
}
; CHECK-LABEL: neg_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .functype neg_v8i16 (v128) -> (v128){{$}}
@ -713,6 +737,18 @@ define <4 x i32> @max_u_v4i32(<4 x i32> %x, <4 x i32> %y) {
ret <4 x i32> %a
}
; CHECK-LABEL: abs_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .functype abs_v4i32 (v128) -> (v128){{$}}
; SIMD128-NEXT: i32x4.abs $push[[R:[0-9]+]]=, $0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i32> @abs_v4i32(<4 x i32> %x) {
%a = sub <4 x i32> zeroinitializer, %x
%b = icmp slt <4 x i32> %x, zeroinitializer
%c = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %x
ret <4 x i32> %c
}
; CHECK-LABEL: neg_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .functype neg_v4i32 (v128) -> (v128){{$}}

9
llvm/test/MC/WebAssembly/simd-encodings.s
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@ -580,6 +580,15 @@ main:
# CHECK: i32x4.dot_i16x8_s # encoding: [0xfd,0xdb,0x01]
i32x4.dot_i16x8_s
# CHECK: i8x16.abs # encoding: [0xfd,0xe1,0x01]
i8x16.abs
# CHECK: i16x8.abs # encoding: [0xfd,0xe2,0x01]
i16x8.abs
# CHECK: i32x4.abs # encoding: [0xfd,0xe3,0x01]
i32x4.abs
# CHECK: i8x16.bitmask # encoding: [0xfd,0xe4,0x01]
i8x16.bitmask