forked from OSchip/llvm-project
parent
254ee9f335
commit
34da52a894
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@ -4142,7 +4142,7 @@ static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
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return false;
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unsigned EltSize = VT.getVectorElementType().getSizeInBits();
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bool symetricMaskRequired =
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bool symmetricMaskRequired =
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(VT.getSizeInBits() >= 256) && (EltSize == 32);
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// VSHUFPSY divides the resulting vector into 4 chunks.
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@ -4175,7 +4175,7 @@ static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
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// For VSHUFPSY, the mask of the second half must be the same as the
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// first but with the appropriate offsets. This works in the same way as
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// VPERMILPS works with masks.
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if (!symetricMaskRequired || Idx < 0)
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if (!symmetricMaskRequired || Idx < 0)
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continue;
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if (MaskVal[i] < 0) {
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MaskVal[i] = Idx - l;
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@ -4603,7 +4603,7 @@ static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
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return (FstHalf | (SndHalf << 4));
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}
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// Symetric in-lane mask. Each lane has 4 elements (for imm8)
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// Symmetric in-lane mask. Each lane has 4 elements (for imm8)
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static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
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unsigned EltSize = VT.getVectorElementType().getSizeInBits();
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if (EltSize < 32)
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@ -4652,7 +4652,7 @@ static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
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unsigned EltSize = VT.getVectorElementType().getSizeInBits();
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if (VT.getSizeInBits() < 256 || EltSize < 32)
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return false;
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bool symetricMaskRequired = (EltSize == 32);
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bool symmetricMaskRequired = (EltSize == 32);
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unsigned NumElts = VT.getVectorNumElements();
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unsigned NumLanes = VT.getSizeInBits()/128;
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@ -4664,7 +4664,7 @@ static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
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for (unsigned i = 0; i != LaneSize; ++i) {
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if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
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return false;
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if (symetricMaskRequired) {
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if (symmetricMaskRequired) {
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if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
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ExpectedMaskVal[i] = Mask[i+l] - l;
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continue;
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