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[DAGCombiner] add fold for 'All sign bits set?' 

(and (setlt X,  0), (setlt Y,  0)) --> (setlt (and X, Y),  0)

We have 7 similar folds, but this one got away. The fact that the
x86 test with a branch didn't change is probably a separate bug. We
may also be missing this and the related folds in instcombine.

llvm-svn: 299252
This commit is contained in:
Sanjay Patel 2017-03-31 20:28:06 +00:00
parent 4c08fe2841
commit 34da36e74f
3 changed files with 12 additions and 16 deletions
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6
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -3214,8 +3214,10 @@ SDValue DAGCombiner::foldAndOfSetCCs(SDValue N0, SDValue N1, const SDLoc &DL) {
// All bits set?
// (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1)
// TODO: All sign bits set?
if (isAllOnesConstant(LR) && CC1 == ISD::SETEQ) {
// All sign bits set?
// (and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0)
if ((isAllOnesConstant(LR) && CC1 == ISD::SETEQ) ||
(isNullConstant(LR) && CC1 == ISD::SETLT)) {
SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
AddToWorklist(And.getNode());
return DAG.getSetCC(DL, VT, And, LR, CC1);

14
llvm/test/CodeGen/PowerPC/setcc-logic.ll
View File

@ -45,11 +45,8 @@ define zeroext i1 @all_bits_set(i32 %P, i32 %Q) {
define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) {
; CHECK-LABEL: all_sign_bits_set:
; CHECK: # BB#0:
; CHECK-NEXT: cmpwi 0, 3, 0
; CHECK-NEXT: cmpwi 1, 4, 0
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: crnand 20, 0, 4
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: srwi 3, 3, 31
; CHECK-NEXT: blr
%a = icmp slt i32 %P, 0
%b = icmp slt i32 %Q, 0
@ -188,10 +185,9 @@ return:
define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q) {
; CHECK-LABEL: all_sign_bits_set_branch:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cmpwi 0, 3, 0
; CHECK-NEXT: cmpwi 1, 4, 0
; CHECK-NEXT: crand 20, 0, 4
; CHECK-NEXT: bc 4, 20, .LBB11_2
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: cmpwi 0, 3, -1
; CHECK-NEXT: bgt 0, .LBB11_2
; CHECK-NEXT: # BB#1: # %bb1
; CHECK-NEXT: li 3, 4
; CHECK-NEXT: blr

8
llvm/test/CodeGen/X86/setcc-logic.ll
View File

@ -41,11 +41,9 @@ define zeroext i1 @all_bits_set(i32 %P, i32 %Q) nounwind {
define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) nounwind {
; CHECK-LABEL: all_sign_bits_set:
; CHECK: # BB#0:
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: sets %cl
; CHECK-NEXT: testl %esi, %esi
; CHECK-NEXT: sets %al
; CHECK-NEXT: andb %cl, %al
; CHECK-NEXT: andl %esi, %edi
; CHECK-NEXT: shrl $31, %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
%a = icmp slt i32 %P, 0
%b = icmp slt i32 %Q, 0