forked from OSchip/llvm-project
AMDGPU: Add option to expand 64-bit integer division in IR
I didn't realize we were already expanding 24/32-bit division here already. Use the available IntegerDivision utilities. This uses loops, so produces significantly smaller code than the inline DAG expansion. This now requires width reductions of 64-bit divisions before introducing the expanded loops. This helps work around missing legalization in GlobalISel for division, which are the only remaining core instructions that didn't work at all. I think this is plausibly a better implementation than exists in the DAG, although turning it on by default misses out on the constant value optimizations and also needs benchmarking.
This commit is contained in:
Matt Arsenault
parent
391cc4dd41
commit
34d9a16e54
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@ -39,6 +39,7 @@
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#include "llvm/IR/Operator.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#include "llvm/Transforms/Utils/IntegerDivision.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Casting.h"
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@ -63,6 +64,12 @@ static cl::opt<bool> UseMul24Intrin(
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cl::ReallyHidden,
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cl::init(true));
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static cl::opt<bool> ExpandDiv64InIR(
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"amdgpu-codegenprepare-expand-div64",
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cl::desc("Expand 64-bit division in AMDGPUCodeGenPrepare"),
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cl::ReallyHidden,
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cl::init(false));
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class AMDGPUCodeGenPrepare : public FunctionPass,
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public InstVisitor<AMDGPUCodeGenPrepare, bool> {
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const GCNSubtarget *ST = nullptr;
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@ -160,16 +167,27 @@ class AMDGPUCodeGenPrepare : public FunctionPass,
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bool divHasSpecialOptimization(BinaryOperator &I,
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Value *Num, Value *Den) const;
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int getDivNumBits(BinaryOperator &I,
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Value *Num, Value *Den,
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unsigned AtLeast, bool Signed) const;
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/// Expands 24 bit div or rem.
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Value* expandDivRem24(IRBuilder<> &Builder, BinaryOperator &I,
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Value *Num, Value *Den,
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bool IsDiv, bool IsSigned) const;
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Value *expandDivRem24Impl(IRBuilder<> &Builder, BinaryOperator &I,
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Value *Num, Value *Den, unsigned NumBits,
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bool IsDiv, bool IsSigned) const;
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/// Expands 32 bit div or rem.
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Value* expandDivRem32(IRBuilder<> &Builder, BinaryOperator &I,
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Value *Num, Value *Den) const;
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Value *shrinkDivRem64(IRBuilder<> &Builder, BinaryOperator &I,
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Value *Num, Value *Den) const;
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void expandDivRem64(BinaryOperator &I) const;
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/// Widen a scalar load.
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///
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/// \details \p Widen scalar load for uniform, small type loads from constant
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@ -806,30 +824,49 @@ static Value* getMulHu(IRBuilder<> &Builder, Value *LHS, Value *RHS) {
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return getMul64(Builder, LHS, RHS).second;
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}
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/// Figure out how many bits are really needed for this ddivision. \p AtLeast is
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/// an optimization hint to bypass the second ComputeNumSignBits call if we the
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/// first one is insufficient. Returns -1 on failure.
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int AMDGPUCodeGenPrepare::getDivNumBits(BinaryOperator &I,
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Value *Num, Value *Den,
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unsigned AtLeast, bool IsSigned) const {
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const DataLayout &DL = Mod->getDataLayout();
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unsigned LHSSignBits = ComputeNumSignBits(Num, DL, 0, AC, &I);
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if (LHSSignBits < AtLeast)
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return -1;
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unsigned RHSSignBits = ComputeNumSignBits(Den, DL, 0, AC, &I);
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if (RHSSignBits < AtLeast)
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return -1;
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unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
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unsigned DivBits = Num->getType()->getScalarSizeInBits() - SignBits;
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if (IsSigned)
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++DivBits;
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return DivBits;
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}
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// The fractional part of a float is enough to accurately represent up to
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// a 24-bit signed integer.
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Value* AMDGPUCodeGenPrepare::expandDivRem24(IRBuilder<> &Builder,
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Value *AMDGPUCodeGenPrepare::expandDivRem24(IRBuilder<> &Builder,
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BinaryOperator &I,
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Value *Num, Value *Den,
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bool IsDiv, bool IsSigned) const {
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assert(Num->getType()->isIntegerTy(32));
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const DataLayout &DL = Mod->getDataLayout();
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unsigned LHSSignBits = ComputeNumSignBits(Num, DL, 0, AC, &I);
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if (LHSSignBits < 9)
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int DivBits = getDivNumBits(I, Num, Den, 9, IsSigned);
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if (DivBits == -1)
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return nullptr;
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return expandDivRem24Impl(Builder, I, Num, Den, DivBits, IsDiv, IsSigned);
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}
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unsigned RHSSignBits = ComputeNumSignBits(Den, DL, 0, AC, &I);
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if (RHSSignBits < 9)
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return nullptr;
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unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
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unsigned DivBits = 32 - SignBits;
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if (IsSigned)
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++DivBits;
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Value *AMDGPUCodeGenPrepare::expandDivRem24Impl(IRBuilder<> &Builder,
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BinaryOperator &I,
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Value *Num, Value *Den,
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unsigned DivBits,
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bool IsDiv, bool IsSigned) const {
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Type *I32Ty = Builder.getInt32Ty();
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Num = Builder.CreateTrunc(Num, I32Ty);
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Den = Builder.CreateTrunc(Den, I32Ty);
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Type *F32Ty = Builder.getFloatTy();
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ConstantInt *One = Builder.getInt32(1);
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Value *JQ = One;
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@ -901,14 +938,19 @@ Value* AMDGPUCodeGenPrepare::expandDivRem24(IRBuilder<> &Builder,
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Res = Builder.CreateSub(Num, Rem);
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}
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if (DivBits != 0 && DivBits < 32) {
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// Extend in register from the number of bits this divide really is.
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if (IsSigned) {
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Res = Builder.CreateShl(Res, 32 - DivBits);
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Res = Builder.CreateAShr(Res, 32 - DivBits);
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int InRegBits = 32 - DivBits;
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Res = Builder.CreateShl(Res, InRegBits);
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Res = Builder.CreateAShr(Res, InRegBits);
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} else {
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ConstantInt *TruncMask = Builder.getInt32((UINT64_C(1) << DivBits) - 1);
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ConstantInt *TruncMask
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= Builder.getInt32((UINT64_C(1) << DivBits) - 1);
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Res = Builder.CreateAnd(Res, TruncMask);
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}
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}
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return Res;
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}
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@ -981,8 +1023,8 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder,
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}
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if (Value *Res = expandDivRem24(Builder, I, Num, Den, IsDiv, IsSigned)) {
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Res = Builder.CreateTrunc(Res, Ty);
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return Res;
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return IsSigned ? Builder.CreateSExtOrTrunc(Res, Ty) :
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Builder.CreateZExtOrTrunc(Res, Ty);
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}
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ConstantInt *Zero = Builder.getInt32(0);
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@ -1093,6 +1135,53 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder,
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return Res;
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}
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Value *AMDGPUCodeGenPrepare::shrinkDivRem64(IRBuilder<> &Builder,
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BinaryOperator &I,
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Value *Num, Value *Den) const {
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if (!ExpandDiv64InIR && divHasSpecialOptimization(I, Num, Den))
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return nullptr; // Keep it for later optimization.
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Instruction::BinaryOps Opc = I.getOpcode();
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bool IsDiv = Opc == Instruction::SDiv || Opc == Instruction::UDiv;
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bool IsSigned = Opc == Instruction::SDiv || Opc == Instruction::SRem;
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int NumDivBits = getDivNumBits(I, Num, Den, 32, IsSigned);
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if (NumDivBits == -1)
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return nullptr;
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Value *Narrowed = nullptr;
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if (NumDivBits <= 24) {
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Narrowed = expandDivRem24Impl(Builder, I, Num, Den, NumDivBits,
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IsDiv, IsSigned);
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} else if (NumDivBits <= 32) {
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Narrowed = expandDivRem32(Builder, I, Num, Den);
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}
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if (Narrowed) {
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return IsSigned ? Builder.CreateSExt(Narrowed, Num->getType()) :
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Builder.CreateZExt(Narrowed, Num->getType());
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}
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return nullptr;
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}
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void AMDGPUCodeGenPrepare::expandDivRem64(BinaryOperator &I) const {
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Instruction::BinaryOps Opc = I.getOpcode();
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// Do the general expansion.
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if (Opc == Instruction::UDiv || Opc == Instruction::SDiv) {
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expandDivisionUpTo64Bits(&I);
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return;
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}
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if (Opc == Instruction::URem || Opc == Instruction::SRem) {
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expandRemainderUpTo64Bits(&I);
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return;
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}
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llvm_unreachable("not a division");
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}
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bool AMDGPUCodeGenPrepare::visitBinaryOperator(BinaryOperator &I) {
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if (foldBinOpIntoSelect(I))
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return true;
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@ -1108,9 +1197,13 @@ bool AMDGPUCodeGenPrepare::visitBinaryOperator(BinaryOperator &I) {
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Instruction::BinaryOps Opc = I.getOpcode();
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Type *Ty = I.getType();
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Value *NewDiv = nullptr;
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unsigned ScalarSize = Ty->getScalarSizeInBits();
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SmallVector<BinaryOperator *, 8> Div64ToExpand;
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if ((Opc == Instruction::URem || Opc == Instruction::UDiv ||
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Opc == Instruction::SRem || Opc == Instruction::SDiv) &&
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Ty->getScalarSizeInBits() <= 32) {
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ScalarSize <= 64) {
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Value *Num = I.getOperand(0);
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Value *Den = I.getOperand(1);
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IRBuilder<> Builder(&I);
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@ -1122,13 +1215,35 @@ bool AMDGPUCodeGenPrepare::visitBinaryOperator(BinaryOperator &I) {
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for (unsigned N = 0, E = VT->getNumElements(); N != E; ++N) {
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Value *NumEltN = Builder.CreateExtractElement(Num, N);
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Value *DenEltN = Builder.CreateExtractElement(Den, N);
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Value *NewElt = expandDivRem32(Builder, I, NumEltN, DenEltN);
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Value *NewElt;
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if (ScalarSize <= 32) {
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NewElt = expandDivRem32(Builder, I, NumEltN, DenEltN);
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if (!NewElt)
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NewElt = Builder.CreateBinOp(Opc, NumEltN, DenEltN);
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} else {
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// See if this 64-bit division can be shrunk to 32/24-bits before
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// producing the general expansion.
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NewElt = shrinkDivRem64(Builder, I, NumEltN, DenEltN);
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if (!NewElt) {
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// The general 64-bit expansion introduces control flow and doesn't
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// return the new value. Just insert a scalar copy and defer
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// expanding it.
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NewElt = Builder.CreateBinOp(Opc, NumEltN, DenEltN);
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Div64ToExpand.push_back(cast<BinaryOperator>(NewElt));
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}
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}
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NewDiv = Builder.CreateInsertElement(NewDiv, NewElt, N);
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}
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} else {
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if (ScalarSize <= 32)
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NewDiv = expandDivRem32(Builder, I, Num, Den);
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else {
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NewDiv = shrinkDivRem64(Builder, I, Num, Den);
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if (!NewDiv)
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Div64ToExpand.push_back(&I);
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}
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}
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if (NewDiv) {
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@ -1138,6 +1253,14 @@ bool AMDGPUCodeGenPrepare::visitBinaryOperator(BinaryOperator &I) {
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}
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}
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if (ExpandDiv64InIR) {
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// TODO: We get much worse code in specially handled constant cases.
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for (BinaryOperator *Div : Div64ToExpand) {
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expandDivRem64(*Div);
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Changed = true;
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}
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}
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return Changed;
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}
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@ -1255,11 +1378,25 @@ bool AMDGPUCodeGenPrepare::runOnFunction(Function &F) {
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bool MadeChange = false;
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for (BasicBlock &BB : F) {
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Function::iterator NextBB;
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for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; FI = NextBB) {
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BasicBlock *BB = &*FI;
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NextBB = std::next(FI);
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BasicBlock::iterator Next;
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for (BasicBlock::iterator I = BB.begin(), E = BB.end(); I != E; I = Next) {
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for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; I = Next) {
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Next = std::next(I);
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MadeChange |= visit(*I);
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if (Next != E) { // Control flow changed
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BasicBlock *NextInstBB = Next->getParent();
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if (NextInstBB != BB) {
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BB = NextInstBB;
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E = BB->end();
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FE = F.end();
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}
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}
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}
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}
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@ -5505,8 +5505,13 @@ define amdgpu_kernel void @udiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %
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define amdgpu_kernel void @udiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
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; CHECK-LABEL: @udiv_v2i64_pow2k_denom(
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; CHECK-NEXT: [[R:%.*]] = udiv <2 x i64> [[X:%.*]], <i64 4096, i64 4096>
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; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
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; CHECK-NEXT: [[TMP2:%.*]] = udiv i64 [[TMP1]], 4096
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
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; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
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; CHECK-NEXT: [[TMP5:%.*]] = udiv i64 [[TMP4]], 4096
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
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; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]]
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; CHECK-NEXT: ret void
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;
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; GCN-LABEL: udiv_v2i64_pow2k_denom:
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@ -5516,8 +5521,8 @@ define amdgpu_kernel void @udiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out,
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], 12
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; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 12
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; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], 12
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_mov_b32_e32 v1, s1
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; GCN-NEXT: v_mov_b32_e32 v2, s2
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@ -5531,8 +5536,13 @@ define amdgpu_kernel void @udiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out,
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define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
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; CHECK-LABEL: @udiv_v2i64_mixed_pow2k_denom(
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; CHECK-NEXT: [[R:%.*]] = udiv <2 x i64> [[X:%.*]], <i64 4096, i64 4095>
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; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
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; CHECK-NEXT: [[TMP2:%.*]] = udiv i64 [[TMP1]], 4096
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
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; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
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; CHECK-NEXT: [[TMP5:%.*]] = udiv i64 [[TMP4]], 4095
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
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; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]]
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; CHECK-NEXT: ret void
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;
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; GCN-LABEL: udiv_v2i64_mixed_pow2k_denom:
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@ -5540,7 +5550,7 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)*
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; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
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; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000
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; GCN-NEXT: v_rcp_f32_e32 v0, v0
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; GCN-NEXT: s_movk_i32 s4, 0xf001
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; GCN-NEXT: s_movk_i32 s6, 0xf001
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; GCN-NEXT: v_mov_b32_e32 v7, 0
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; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
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@ -5549,11 +5559,13 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)*
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; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
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; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
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; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
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; GCN-NEXT: s_movk_i32 s0, 0xfff
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; GCN-NEXT: v_mul_hi_u32 v3, v0, s6
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; GCN-NEXT: v_mul_lo_u32 v5, v1, s6
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; GCN-NEXT: v_mul_lo_u32 v4, v0, s6
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: v_mul_hi_u32 v3, v0, s4
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; GCN-NEXT: v_mul_lo_u32 v5, v1, s4
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; GCN-NEXT: v_mul_lo_u32 v4, v0, s4
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; GCN-NEXT: v_subrev_i32_e32 v3, vcc, v0, v3
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; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
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; GCN-NEXT: v_mul_hi_u32 v6, v0, v4
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@ -5571,19 +5583,17 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)*
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; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
|
||||
; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v3
|
||||
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
|
||||
; GCN-NEXT: v_mul_hi_u32 v5, v0, s4
|
||||
; GCN-NEXT: v_mul_hi_u32 v5, v0, s6
|
||||
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]
|
||||
; GCN-NEXT: v_mul_lo_u32 v6, v3, s4
|
||||
; GCN-NEXT: v_mul_lo_u32 v8, v0, s4
|
||||
; GCN-NEXT: v_mul_lo_u32 v6, v3, s6
|
||||
; GCN-NEXT: v_mul_lo_u32 v8, v0, s6
|
||||
; GCN-NEXT: v_subrev_i32_e32 v5, vcc, v0, v5
|
||||
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
|
||||
; GCN-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
|
||||
; GCN-NEXT: v_mul_lo_u32 v6, v0, v5
|
||||
; GCN-NEXT: v_mul_hi_u32 v9, v0, v8
|
||||
; GCN-NEXT: v_mul_hi_u32 v10, v0, v5
|
||||
; GCN-NEXT: v_mul_hi_u32 v11, v3, v5
|
||||
; GCN-NEXT: s_movk_i32 s0, 0xfff
|
||||
; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6
|
||||
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v10, v3, v8
|
||||
|
|
@ -5608,6 +5618,7 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)*
|
|||
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v5, s11, v0
|
||||
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
|
||||
; GCN-NEXT: s_lshr_b64 s[2:3], s[8:9], 12
|
||||
; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
|
||||
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc
|
||||
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v6, v2, vcc
|
||||
|
|
@ -5641,9 +5652,8 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)*
|
|||
; GCN-NEXT: v_cndmask_b32_e64 v3, v1, v3, s[0:1]
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1]
|
||||
; GCN-NEXT: s_lshr_b64 s[0:1], s[8:9], 12
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
||||
; GCN-NEXT: s_endpgm
|
||||
%r = udiv <2 x i64> %x, <i64 4096, i64 4095>
|
||||
|
|
@ -5654,8 +5664,15 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)*
|
|||
define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
|
||||
; CHECK-LABEL: @udiv_v2i64_pow2_shl_denom(
|
||||
; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
|
||||
; CHECK-NEXT: [[R:%.*]] = udiv <2 x i64> [[X:%.*]], [[SHL_Y]]
|
||||
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = udiv i64 [[TMP1]], [[TMP2]]
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = udiv i64 [[TMP5]], [[TMP6]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
|
||||
; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
; GCN-LABEL: udiv_v2i64_pow2_shl_denom:
|
||||
|
|
@ -5666,10 +5683,10 @@ define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_add_i32 s1, s2, 12
|
||||
; GCN-NEXT: s_add_i32 s0, s0, 12
|
||||
; GCN-NEXT: s_lshr_b64 s[2:3], s[10:11], s1
|
||||
; GCN-NEXT: s_add_i32 s2, s2, 12
|
||||
; GCN-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
|
||||
; GCN-NEXT: s_lshr_b64 s[2:3], s[10:11], s2
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, s2
|
||||
|
|
@ -5874,8 +5891,13 @@ define amdgpu_kernel void @urem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %
|
|||
|
||||
define amdgpu_kernel void @urem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
|
||||
; CHECK-LABEL: @urem_v2i64_pow2k_denom(
|
||||
; CHECK-NEXT: [[R:%.*]] = urem <2 x i64> [[X:%.*]], <i64 4096, i64 4096>
|
||||
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = urem i64 [[TMP1]], 4096
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = urem i64 [[TMP4]], 4096
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
|
||||
; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
; GCN-LABEL: urem_v2i64_pow2k_denom:
|
||||
|
|
@ -5887,8 +5909,8 @@ define amdgpu_kernel void @urem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out,
|
|||
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_and_b32 s1, s2, s8
|
||||
; GCN-NEXT: s_and_b32 s0, s0, s8
|
||||
; GCN-NEXT: s_and_b32 s1, s2, s8
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, s1
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, v1
|
||||
|
|
@ -5902,8 +5924,15 @@ define amdgpu_kernel void @urem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out,
|
|||
define amdgpu_kernel void @urem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
|
||||
; CHECK-LABEL: @urem_v2i64_pow2_shl_denom(
|
||||
; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
|
||||
; CHECK-NEXT: [[R:%.*]] = urem <2 x i64> [[X:%.*]], [[SHL_Y]]
|
||||
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = urem i64 [[TMP1]], [[TMP2]]
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = urem i64 [[TMP5]], [[TMP6]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
|
||||
; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
; GCN-LABEL: urem_v2i64_pow2_shl_denom:
|
||||
|
|
@ -5916,14 +5945,14 @@ define amdgpu_kernel void @urem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_lshl_b64 s[0:1], s[12:13], s0
|
||||
; GCN-NEXT: s_lshl_b64 s[2:3], s[12:13], s2
|
||||
; GCN-NEXT: s_add_u32 s2, s2, -1
|
||||
; GCN-NEXT: s_addc_u32 s3, s3, -1
|
||||
; GCN-NEXT: s_and_b64 s[2:3], s[10:11], s[2:3]
|
||||
; GCN-NEXT: s_lshl_b64 s[0:1], s[12:13], s0
|
||||
; GCN-NEXT: s_add_u32 s0, s0, -1
|
||||
; GCN-NEXT: s_addc_u32 s1, s1, -1
|
||||
; GCN-NEXT: s_and_b64 s[0:1], s[8:9], s[0:1]
|
||||
; GCN-NEXT: s_add_u32 s2, s2, -1
|
||||
; GCN-NEXT: s_addc_u32 s3, s3, -1
|
||||
; GCN-NEXT: s_and_b64 s[2:3], s[10:11], s[2:3]
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, s2
|
||||
|
|
@ -6249,8 +6278,13 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %
|
|||
|
||||
define amdgpu_kernel void @sdiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
|
||||
; CHECK-LABEL: @sdiv_v2i64_pow2k_denom(
|
||||
; CHECK-NEXT: [[R:%.*]] = sdiv <2 x i64> [[X:%.*]], <i64 4096, i64 4096>
|
||||
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = sdiv i64 [[TMP1]], 4096
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = sdiv i64 [[TMP4]], 4096
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
|
||||
; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
; GCN-LABEL: sdiv_v2i64_pow2k_denom:
|
||||
|
|
@ -6260,16 +6294,16 @@ define amdgpu_kernel void @sdiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out,
|
|||
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_ashr_i32 s8, s3, 31
|
||||
; GCN-NEXT: s_lshr_b32 s8, s8, 20
|
||||
; GCN-NEXT: s_add_u32 s2, s2, s8
|
||||
; GCN-NEXT: s_addc_u32 s3, s3, 0
|
||||
; GCN-NEXT: s_ashr_i32 s8, s1, 31
|
||||
; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 12
|
||||
; GCN-NEXT: s_lshr_b32 s8, s8, 20
|
||||
; GCN-NEXT: s_add_u32 s0, s0, s8
|
||||
; GCN-NEXT: s_addc_u32 s1, s1, 0
|
||||
; GCN-NEXT: s_ashr_i32 s8, s3, 31
|
||||
; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 12
|
||||
; GCN-NEXT: s_lshr_b32 s8, s8, 20
|
||||
; GCN-NEXT: s_add_u32 s2, s2, s8
|
||||
; GCN-NEXT: s_addc_u32 s3, s3, 0
|
||||
; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 12
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, s2
|
||||
|
|
@ -6283,101 +6317,112 @@ define amdgpu_kernel void @sdiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out,
|
|||
|
||||
define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
|
||||
; CHECK-LABEL: @ssdiv_v2i64_mixed_pow2k_denom(
|
||||
; CHECK-NEXT: [[R:%.*]] = sdiv <2 x i64> [[X:%.*]], <i64 4096, i64 4095>
|
||||
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = sdiv i64 [[TMP1]], 4096
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = sdiv i64 [[TMP4]], 4095
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
|
||||
; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
; GCN-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
|
||||
; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 0x457ff000
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, 0x4f800000
|
||||
; GCN-NEXT: v_mac_f32_e32 v0, 0, v1
|
||||
; GCN-NEXT: v_rcp_f32_e32 v0, v0
|
||||
; GCN-NEXT: s_movk_i32 s6, 0xf001
|
||||
; GCN-NEXT: v_mov_b32_e32 v7, 0
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, 0
|
||||
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
|
||||
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
|
||||
; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
|
||||
; GCN-NEXT: v_trunc_f32_e32 v1, v1
|
||||
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
|
||||
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
|
||||
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
|
||||
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
|
||||
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-NEXT: v_mul_hi_u32 v3, s6, v0
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, v1, s6
|
||||
; GCN-NEXT: v_mul_lo_u32 v4, v0, s6
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
||||
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v3, v0, v4
|
||||
; GCN-NEXT: v_mul_lo_u32 v6, v0, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v8, v0, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v9, v1, v2
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
|
||||
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
|
||||
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v8, v1, v4
|
||||
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
|
||||
; GCN-NEXT: v_add_i32_e32 v3, vcc, v8, v3
|
||||
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc
|
||||
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
||||
; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2
|
||||
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v4, vcc
|
||||
; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
|
||||
; GCN-NEXT: v_mul_lo_u32 v4, v2, s6
|
||||
; GCN-NEXT: v_mul_hi_u32 v6, s6, v0
|
||||
; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4
|
||||
; GCN-NEXT: v_mul_lo_u32 v6, v0, s6
|
||||
; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4
|
||||
; GCN-NEXT: v_mul_lo_u32 v10, v0, v4
|
||||
; GCN-NEXT: v_mul_hi_u32 v12, v0, v4
|
||||
; GCN-NEXT: v_mul_hi_u32 v11, v0, v6
|
||||
; GCN-NEXT: v_mul_hi_u32 v9, v2, v6
|
||||
; GCN-NEXT: v_mul_lo_u32 v6, v2, v6
|
||||
; GCN-NEXT: v_mul_hi_u32 v8, v2, v4
|
||||
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
|
||||
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v7, v12, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, v2, v4
|
||||
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10
|
||||
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc
|
||||
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v5, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v6, v2
|
||||
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
|
||||
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[2:3]
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_ashr_i32 s2, s11, 31
|
||||
; GCN-NEXT: s_add_u32 s0, s10, s2
|
||||
; GCN-NEXT: s_ashr_i32 s0, s9, 31
|
||||
; GCN-NEXT: s_lshr_b32 s0, s0, 20
|
||||
; GCN-NEXT: v_mul_hi_u32 v2, s6, v0
|
||||
; GCN-NEXT: v_mul_lo_u32 v3, v1, s6
|
||||
; GCN-NEXT: s_add_u32 s2, s8, s0
|
||||
; GCN-NEXT: s_addc_u32 s3, s9, 0
|
||||
; GCN-NEXT: s_ashr_i32 s8, s11, 31
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
|
||||
; GCN-NEXT: v_mul_lo_u32 v3, v0, s6
|
||||
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
|
||||
; GCN-NEXT: v_mul_lo_u32 v4, v0, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v5, v0, v3
|
||||
; GCN-NEXT: v_mul_hi_u32 v7, v1, v2
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
|
||||
; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 12
|
||||
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
|
||||
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v6, v1, v3
|
||||
; GCN-NEXT: v_mul_hi_u32 v3, v1, v3
|
||||
; GCN-NEXT: s_mov_b32 s9, s8
|
||||
; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4
|
||||
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, 0
|
||||
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
||||
; GCN-NEXT: v_mov_b32_e32 v6, 0
|
||||
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
|
||||
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
|
||||
; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
|
||||
; GCN-NEXT: v_mul_lo_u32 v5, v2, s6
|
||||
; GCN-NEXT: v_mul_hi_u32 v7, s6, v0
|
||||
; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
|
||||
; GCN-NEXT: v_mul_lo_u32 v7, v0, s6
|
||||
; GCN-NEXT: v_subrev_i32_e32 v5, vcc, v0, v5
|
||||
; GCN-NEXT: v_mul_lo_u32 v10, v0, v5
|
||||
; GCN-NEXT: v_mul_hi_u32 v12, v0, v5
|
||||
; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
|
||||
; GCN-NEXT: v_mul_hi_u32 v9, v2, v7
|
||||
; GCN-NEXT: v_mul_lo_u32 v7, v2, v7
|
||||
; GCN-NEXT: v_mul_hi_u32 v8, v2, v5
|
||||
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
|
||||
; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, v2, v5
|
||||
; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
|
||||
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
|
||||
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2
|
||||
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
|
||||
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
|
||||
; GCN-NEXT: s_add_u32 s0, s10, s8
|
||||
; GCN-NEXT: s_addc_u32 s1, s11, s8
|
||||
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
|
||||
; GCN-NEXT: s_mov_b32 s3, s2
|
||||
; GCN-NEXT: s_addc_u32 s1, s11, s2
|
||||
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
|
||||
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[8:9]
|
||||
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, s0, v1
|
||||
; GCN-NEXT: v_mul_hi_u32 v3, s0, v0
|
||||
; GCN-NEXT: v_mul_hi_u32 v4, s0, v1
|
||||
; GCN-NEXT: v_mul_hi_u32 v6, s1, v1
|
||||
; GCN-NEXT: v_mul_hi_u32 v5, s0, v1
|
||||
; GCN-NEXT: v_mul_hi_u32 v7, s1, v1
|
||||
; GCN-NEXT: v_mul_lo_u32 v1, s1, v1
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
||||
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v4, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v4, s1, v0
|
||||
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v5, s1, v0
|
||||
; GCN-NEXT: v_mul_hi_u32 v0, s1, v0
|
||||
; GCN-NEXT: s_movk_i32 s3, 0xfff
|
||||
; GCN-NEXT: s_movk_i32 s9, 0xfff
|
||||
; GCN-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
|
||||
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
|
||||
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v6, v5, vcc
|
||||
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
|
||||
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v2, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, v1, s3
|
||||
; GCN-NEXT: v_mul_hi_u32 v3, s3, v0
|
||||
; GCN-NEXT: v_mul_lo_u32 v4, v0, s3
|
||||
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, v1, s9
|
||||
; GCN-NEXT: v_mul_hi_u32 v3, s9, v0
|
||||
; GCN-NEXT: v_mul_lo_u32 v4, v0, s9
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
||||
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s0, v4
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GCN-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc
|
||||
; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s3, v4
|
||||
; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s9, v4
|
||||
; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
|
||||
; GCN-NEXT: s_movk_i32 s0, 0xffe
|
||||
; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3
|
||||
|
|
@ -6394,22 +6439,17 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)*
|
|||
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]
|
||||
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
|
||||
; GCN-NEXT: s_ashr_i32 s0, s9, 31
|
||||
; GCN-NEXT: s_lshr_b32 s0, s0, 20
|
||||
; GCN-NEXT: s_add_u32 s0, s8, s0
|
||||
; GCN-NEXT: s_addc_u32 s1, s9, 0
|
||||
; GCN-NEXT: v_xor_b32_e32 v0, s2, v0
|
||||
; GCN-NEXT: v_xor_b32_e32 v1, s2, v1
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, s2
|
||||
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0
|
||||
; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 12
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
|
||||
; GCN-NEXT: v_xor_b32_e32 v0, s8, v0
|
||||
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0
|
||||
; GCN-NEXT: v_xor_b32_e32 v1, s8, v1
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, s8
|
||||
; GCN-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
||||
; GCN-NEXT: s_endpgm
|
||||
%r = sdiv <2 x i64> %x, <i64 4096, i64 4095>
|
||||
|
|
@ -6420,8 +6460,15 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)*
|
|||
define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
|
||||
; CHECK-LABEL: @sdiv_v2i64_pow2_shl_denom(
|
||||
; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
|
||||
; CHECK-NEXT: [[R:%.*]] = sdiv <2 x i64> [[X:%.*]], [[SHL_Y]]
|
||||
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = sdiv i64 [[TMP1]], [[TMP2]]
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = sdiv i64 [[TMP5]], [[TMP6]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
|
||||
; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
; GCN-LABEL: sdiv_v2i64_pow2_shl_denom:
|
||||
|
|
@ -6432,8 +6479,8 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: s_mov_b32 s18, 0x4f800000
|
||||
; GCN-NEXT: s_mov_b32 s19, 0x5f7ffffc
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_lshl_b64 s[12:13], s[2:3], s4
|
||||
; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s6
|
||||
; GCN-NEXT: s_lshl_b64 s[12:13], s[2:3], s6
|
||||
; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
|
||||
; GCN-NEXT: s_ashr_i32 s16, s3, 31
|
||||
; GCN-NEXT: s_add_u32 s2, s2, s16
|
||||
; GCN-NEXT: s_mov_b32 s17, s16
|
||||
|
|
@ -6503,22 +6550,22 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
|
||||
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_ashr_i32 s2, s11, 31
|
||||
; GCN-NEXT: s_add_u32 s0, s10, s2
|
||||
; GCN-NEXT: s_ashr_i32 s2, s9, 31
|
||||
; GCN-NEXT: s_add_u32 s0, s8, s2
|
||||
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
|
||||
; GCN-NEXT: s_mov_b32 s3, s2
|
||||
; GCN-NEXT: s_addc_u32 s1, s11, s2
|
||||
; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[2:3]
|
||||
; GCN-NEXT: s_addc_u32 s1, s9, s2
|
||||
; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[2:3]
|
||||
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, s10, v1
|
||||
; GCN-NEXT: v_mul_hi_u32 v3, s10, v0
|
||||
; GCN-NEXT: v_mul_hi_u32 v5, s10, v1
|
||||
; GCN-NEXT: v_mul_hi_u32 v7, s11, v1
|
||||
; GCN-NEXT: v_mul_lo_u32 v1, s11, v1
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, s8, v1
|
||||
; GCN-NEXT: v_mul_hi_u32 v3, s8, v0
|
||||
; GCN-NEXT: v_mul_hi_u32 v5, s8, v1
|
||||
; GCN-NEXT: v_mul_hi_u32 v7, s9, v1
|
||||
; GCN-NEXT: v_mul_lo_u32 v1, s9, v1
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
||||
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v5, s11, v0
|
||||
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
|
||||
; GCN-NEXT: v_mul_lo_u32 v5, s9, v0
|
||||
; GCN-NEXT: v_mul_hi_u32 v0, s9, v0
|
||||
; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[16:17]
|
||||
; GCN-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
|
||||
|
|
@ -6533,8 +6580,8 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
||||
; GCN-NEXT: v_mul_lo_u32 v3, s14, v0
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
|
||||
; GCN-NEXT: v_sub_i32_e32 v5, vcc, s11, v2
|
||||
; GCN-NEXT: v_sub_i32_e32 v3, vcc, s10, v3
|
||||
; GCN-NEXT: v_sub_i32_e32 v5, vcc, s9, v2
|
||||
; GCN-NEXT: v_sub_i32_e32 v3, vcc, s8, v3
|
||||
; GCN-NEXT: v_subb_u32_e64 v5, s[0:1], v5, v7, vcc
|
||||
; GCN-NEXT: v_subrev_i32_e64 v7, s[0:1], s14, v3
|
||||
; GCN-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]
|
||||
|
|
@ -6548,14 +6595,14 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
|
||||
; GCN-NEXT: v_add_i32_e64 v9, s[0:1], 1, v0
|
||||
; GCN-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v1, s[0:1]
|
||||
; GCN-NEXT: s_ashr_i32 s10, s13, 31
|
||||
; GCN-NEXT: s_ashr_i32 s8, s13, 31
|
||||
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
|
||||
; GCN-NEXT: s_add_u32 s12, s12, s10
|
||||
; GCN-NEXT: s_add_u32 s12, s12, s8
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v5, v10, v8, s[0:1]
|
||||
; GCN-NEXT: v_mov_b32_e32 v8, s11
|
||||
; GCN-NEXT: s_mov_b32 s11, s10
|
||||
; GCN-NEXT: s_addc_u32 s13, s13, s10
|
||||
; GCN-NEXT: s_xor_b64 s[12:13], s[12:13], s[10:11]
|
||||
; GCN-NEXT: v_mov_b32_e32 v8, s9
|
||||
; GCN-NEXT: s_mov_b32 s9, s8
|
||||
; GCN-NEXT: s_addc_u32 s13, s13, s8
|
||||
; GCN-NEXT: s_xor_b64 s[12:13], s[12:13], s[8:9]
|
||||
; GCN-NEXT: v_cvt_f32_u32_e32 v10, s12
|
||||
; GCN-NEXT: v_cvt_f32_u32_e32 v11, s13
|
||||
; GCN-NEXT: v_subb_u32_e32 v2, vcc, v8, v2, vcc
|
||||
|
|
@ -6624,42 +6671,42 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: v_add_i32_e32 v3, vcc, v9, v3
|
||||
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v6, v8, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
|
||||
; GCN-NEXT: s_ashr_i32 s14, s9, 31
|
||||
; GCN-NEXT: s_ashr_i32 s14, s11, 31
|
||||
; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
|
||||
; GCN-NEXT: s_add_u32 s0, s8, s14
|
||||
; GCN-NEXT: s_add_u32 s0, s10, s14
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
|
||||
; GCN-NEXT: s_mov_b32 s15, s14
|
||||
; GCN-NEXT: s_addc_u32 s1, s9, s14
|
||||
; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[14:15]
|
||||
; GCN-NEXT: s_addc_u32 s1, s11, s14
|
||||
; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15]
|
||||
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v5, s8, v3
|
||||
; GCN-NEXT: v_mul_hi_u32 v7, s8, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v9, s8, v3
|
||||
; GCN-NEXT: v_mul_hi_u32 v10, s9, v3
|
||||
; GCN-NEXT: v_mul_lo_u32 v3, s9, v3
|
||||
; GCN-NEXT: v_mul_lo_u32 v5, s10, v3
|
||||
; GCN-NEXT: v_mul_hi_u32 v7, s10, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v9, s10, v3
|
||||
; GCN-NEXT: v_mul_hi_u32 v10, s11, v3
|
||||
; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
|
||||
; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
|
||||
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v9, s9, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v2, s9, v2
|
||||
; GCN-NEXT: v_mul_lo_u32 v9, s11, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v2, s11, v2
|
||||
; GCN-NEXT: v_mov_b32_e32 v8, s3
|
||||
; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5
|
||||
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc
|
||||
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v5, vcc, v2, v3
|
||||
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v6, s12, v4
|
||||
; GCN-NEXT: v_mul_hi_u32 v7, s12, v5
|
||||
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0
|
||||
; GCN-NEXT: v_mul_lo_u32 v0, s13, v5
|
||||
; GCN-NEXT: v_subb_u32_e32 v3, vcc, v1, v8, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v1, vcc, v7, v6
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
|
||||
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v4, s12, v3
|
||||
; GCN-NEXT: v_mul_hi_u32 v5, s12, v2
|
||||
; GCN-NEXT: v_mul_lo_u32 v6, s13, v2
|
||||
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
|
||||
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
|
||||
; GCN-NEXT: v_mul_lo_u32 v5, s12, v2
|
||||
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
|
||||
; GCN-NEXT: v_sub_i32_e32 v6, vcc, s11, v4
|
||||
; GCN-NEXT: v_mov_b32_e32 v7, s13
|
||||
; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
|
||||
; GCN-NEXT: v_mul_lo_u32 v1, s12, v5
|
||||
; GCN-NEXT: v_sub_i32_e32 v6, vcc, s9, v0
|
||||
; GCN-NEXT: v_sub_i32_e32 v1, vcc, s8, v1
|
||||
; GCN-NEXT: v_sub_i32_e32 v5, vcc, s10, v5
|
||||
; GCN-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc
|
||||
; GCN-NEXT: v_subrev_i32_e64 v7, s[0:1], s12, v1
|
||||
; GCN-NEXT: v_subrev_i32_e64 v7, s[0:1], s12, v5
|
||||
; GCN-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
|
||||
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v6
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
|
||||
|
|
@ -6667,30 +6714,30 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v6
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1]
|
||||
; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 2, v5
|
||||
; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v4, s[0:1]
|
||||
; GCN-NEXT: v_add_i32_e64 v9, s[0:1], 1, v5
|
||||
; GCN-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v4, s[0:1]
|
||||
; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 2, v2
|
||||
; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v3, s[0:1]
|
||||
; GCN-NEXT: v_add_i32_e64 v9, s[0:1], 1, v2
|
||||
; GCN-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1]
|
||||
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1]
|
||||
; GCN-NEXT: v_mov_b32_e32 v8, s9
|
||||
; GCN-NEXT: v_subb_u32_e32 v0, vcc, v8, v0, vcc
|
||||
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v0
|
||||
; GCN-NEXT: v_mov_b32_e32 v8, s11
|
||||
; GCN-NEXT: v_subb_u32_e32 v4, vcc, v8, v4, vcc
|
||||
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v4
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
|
||||
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v1
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
|
||||
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v0
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
|
||||
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v1, v9, v7, s[0:1]
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
|
||||
; GCN-NEXT: s_xor_b64 s[0:1], s[14:15], s[10:11]
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
|
||||
; GCN-NEXT: v_xor_b32_e32 v1, s0, v1
|
||||
; GCN-NEXT: v_xor_b32_e32 v4, s1, v0
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, s1
|
||||
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v1
|
||||
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v4, v5, vcc
|
||||
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v5
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
|
||||
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v4
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v4, v8, v5, vcc
|
||||
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[0:1]
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
|
||||
; GCN-NEXT: s_xor_b64 s[0:1], s[14:15], s[8:9]
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
|
||||
; GCN-NEXT: v_xor_b32_e32 v2, s0, v2
|
||||
; GCN-NEXT: v_xor_b32_e32 v3, s1, v3
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, s1
|
||||
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s0, v2
|
||||
; GCN-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
|
||||
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
||||
; GCN-NEXT: s_endpgm
|
||||
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
|
||||
|
|
@ -7010,8 +7057,13 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %
|
|||
|
||||
define amdgpu_kernel void @srem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
|
||||
; CHECK-LABEL: @srem_v2i64_pow2k_denom(
|
||||
; CHECK-NEXT: [[R:%.*]] = srem <2 x i64> [[X:%.*]], <i64 4096, i64 4096>
|
||||
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = srem i64 [[TMP1]], 4096
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = srem i64 [[TMP4]], 4096
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
|
||||
; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
; GCN-LABEL: srem_v2i64_pow2k_denom:
|
||||
|
|
@ -7022,20 +7074,20 @@ define amdgpu_kernel void @srem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out,
|
|||
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_ashr_i32 s9, s3, 31
|
||||
; GCN-NEXT: s_lshr_b32 s9, s9, 20
|
||||
; GCN-NEXT: s_add_u32 s9, s2, s9
|
||||
; GCN-NEXT: s_addc_u32 s10, s3, 0
|
||||
; GCN-NEXT: s_and_b32 s9, s9, s8
|
||||
; GCN-NEXT: s_sub_u32 s2, s2, s9
|
||||
; GCN-NEXT: s_subb_u32 s3, s3, s10
|
||||
; GCN-NEXT: s_ashr_i32 s9, s1, 31
|
||||
; GCN-NEXT: s_lshr_b32 s9, s9, 20
|
||||
; GCN-NEXT: s_add_u32 s9, s0, s9
|
||||
; GCN-NEXT: s_addc_u32 s10, s1, 0
|
||||
; GCN-NEXT: s_and_b32 s8, s9, s8
|
||||
; GCN-NEXT: s_sub_u32 s0, s0, s8
|
||||
; GCN-NEXT: s_and_b32 s9, s9, s8
|
||||
; GCN-NEXT: s_sub_u32 s0, s0, s9
|
||||
; GCN-NEXT: s_subb_u32 s1, s1, s10
|
||||
; GCN-NEXT: s_ashr_i32 s9, s3, 31
|
||||
; GCN-NEXT: s_lshr_b32 s9, s9, 20
|
||||
; GCN-NEXT: s_add_u32 s9, s2, s9
|
||||
; GCN-NEXT: s_addc_u32 s10, s3, 0
|
||||
; GCN-NEXT: s_and_b32 s8, s9, s8
|
||||
; GCN-NEXT: s_sub_u32 s2, s2, s8
|
||||
; GCN-NEXT: s_subb_u32 s3, s3, s10
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, s2
|
||||
|
|
@ -7050,8 +7102,15 @@ define amdgpu_kernel void @srem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out,
|
|||
define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
|
||||
; CHECK-LABEL: @srem_v2i64_pow2_shl_denom(
|
||||
; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
|
||||
; CHECK-NEXT: [[R:%.*]] = srem <2 x i64> [[X:%.*]], [[SHL_Y]]
|
||||
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = srem i64 [[TMP1]], [[TMP2]]
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = srem i64 [[TMP5]], [[TMP6]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
|
||||
; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
; GCN-LABEL: srem_v2i64_pow2_shl_denom:
|
||||
|
|
@ -7062,8 +7121,8 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: s_mov_b32 s18, 0x4f800000
|
||||
; GCN-NEXT: s_mov_b32 s19, 0x5f7ffffc
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_lshl_b64 s[14:15], s[2:3], s4
|
||||
; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s6
|
||||
; GCN-NEXT: s_lshl_b64 s[14:15], s[2:3], s6
|
||||
; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
|
||||
; GCN-NEXT: s_ashr_i32 s4, s3, 31
|
||||
; GCN-NEXT: s_add_u32 s2, s2, s4
|
||||
; GCN-NEXT: s_mov_b32 s5, s4
|
||||
|
|
@ -7086,8 +7145,8 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
|
||||
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_ashr_i32 s12, s11, 31
|
||||
; GCN-NEXT: s_add_u32 s0, s10, s12
|
||||
; GCN-NEXT: s_ashr_i32 s12, s9, 31
|
||||
; GCN-NEXT: s_add_u32 s0, s8, s12
|
||||
; GCN-NEXT: v_mul_hi_u32 v3, s6, v0
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, s6, v1
|
||||
; GCN-NEXT: v_mul_lo_u32 v4, s7, v0
|
||||
|
|
@ -7104,8 +7163,8 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v6, v1, v5
|
||||
; GCN-NEXT: v_mul_hi_u32 v5, v1, v5
|
||||
; GCN-NEXT: s_addc_u32 s1, s11, s12
|
||||
; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[12:13]
|
||||
; GCN-NEXT: s_addc_u32 s1, s9, s12
|
||||
; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13]
|
||||
; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
|
||||
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, 0
|
||||
|
|
@ -7140,15 +7199,15 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
|
||||
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
|
||||
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, s10, v1
|
||||
; GCN-NEXT: v_mul_hi_u32 v3, s10, v0
|
||||
; GCN-NEXT: v_mul_hi_u32 v5, s10, v1
|
||||
; GCN-NEXT: v_mul_hi_u32 v7, s11, v1
|
||||
; GCN-NEXT: v_mul_lo_u32 v1, s11, v1
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, s8, v1
|
||||
; GCN-NEXT: v_mul_hi_u32 v3, s8, v0
|
||||
; GCN-NEXT: v_mul_hi_u32 v5, s8, v1
|
||||
; GCN-NEXT: v_mul_hi_u32 v7, s9, v1
|
||||
; GCN-NEXT: v_mul_lo_u32 v1, s9, v1
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
||||
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v5, s11, v0
|
||||
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
|
||||
; GCN-NEXT: v_mul_lo_u32 v5, s9, v0
|
||||
; GCN-NEXT: v_mul_hi_u32 v0, s9, v0
|
||||
; GCN-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
|
||||
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
|
||||
|
|
@ -7161,9 +7220,9 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: v_mul_lo_u32 v0, s16, v0
|
||||
; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
|
||||
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
|
||||
; GCN-NEXT: v_sub_i32_e32 v2, vcc, s11, v1
|
||||
; GCN-NEXT: v_sub_i32_e32 v2, vcc, s9, v1
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, s17
|
||||
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s10, v0
|
||||
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s8, v0
|
||||
; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
|
||||
; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s16, v0
|
||||
; GCN-NEXT: v_subb_u32_e64 v3, s[2:3], v2, v3, s[0:1]
|
||||
|
|
@ -7178,14 +7237,14 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: s_ashr_i32 s2, s15, 31
|
||||
; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
|
||||
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7
|
||||
; GCN-NEXT: s_add_u32 s10, s14, s2
|
||||
; GCN-NEXT: s_add_u32 s8, s14, s2
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, s11
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, s9
|
||||
; GCN-NEXT: s_mov_b32 s3, s2
|
||||
; GCN-NEXT: s_addc_u32 s11, s15, s2
|
||||
; GCN-NEXT: s_xor_b64 s[10:11], s[10:11], s[2:3]
|
||||
; GCN-NEXT: v_cvt_f32_u32_e32 v7, s10
|
||||
; GCN-NEXT: v_cvt_f32_u32_e32 v9, s11
|
||||
; GCN-NEXT: s_addc_u32 s9, s15, s2
|
||||
; GCN-NEXT: s_xor_b64 s[8:9], s[8:9], s[2:3]
|
||||
; GCN-NEXT: v_cvt_f32_u32_e32 v7, s8
|
||||
; GCN-NEXT: v_cvt_f32_u32_e32 v9, s9
|
||||
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc
|
||||
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s17, v1
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
|
||||
|
|
@ -7204,13 +7263,13 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: v_mac_f32_e32 v3, s21, v5
|
||||
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
|
||||
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
|
||||
; GCN-NEXT: s_sub_u32 s2, 0, s10
|
||||
; GCN-NEXT: s_sub_u32 s2, 0, s8
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
||||
; GCN-NEXT: v_mul_hi_u32 v2, s2, v3
|
||||
; GCN-NEXT: v_mul_lo_u32 v7, s2, v5
|
||||
; GCN-NEXT: s_subb_u32 s3, 0, s11
|
||||
; GCN-NEXT: s_subb_u32 s3, 0, s9
|
||||
; GCN-NEXT: v_mul_lo_u32 v8, s3, v3
|
||||
; GCN-NEXT: s_ashr_i32 s14, s9, 31
|
||||
; GCN-NEXT: s_ashr_i32 s14, s11, 31
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7
|
||||
; GCN-NEXT: v_mul_lo_u32 v7, s2, v3
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v8
|
||||
|
|
@ -7255,68 +7314,68 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
|
|||
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v6, v8, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
|
||||
; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
|
||||
; GCN-NEXT: s_add_u32 s0, s8, s14
|
||||
; GCN-NEXT: s_add_u32 s0, s10, s14
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
|
||||
; GCN-NEXT: s_addc_u32 s1, s9, s14
|
||||
; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[14:15]
|
||||
; GCN-NEXT: s_addc_u32 s1, s11, s14
|
||||
; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15]
|
||||
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v5, s8, v3
|
||||
; GCN-NEXT: v_mul_hi_u32 v7, s8, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v9, s8, v3
|
||||
; GCN-NEXT: v_mul_hi_u32 v10, s9, v3
|
||||
; GCN-NEXT: v_mul_lo_u32 v3, s9, v3
|
||||
; GCN-NEXT: v_mul_lo_u32 v5, s10, v3
|
||||
; GCN-NEXT: v_mul_hi_u32 v7, s10, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v9, s10, v3
|
||||
; GCN-NEXT: v_mul_hi_u32 v10, s11, v3
|
||||
; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
|
||||
; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
|
||||
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v9, s9, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v2, s9, v2
|
||||
; GCN-NEXT: v_mul_lo_u32 v9, s11, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v2, s11, v2
|
||||
; GCN-NEXT: v_mov_b32_e32 v8, s12
|
||||
; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5
|
||||
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc
|
||||
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v5, vcc, v2, v3
|
||||
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v6, v4, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v4, s10, v2
|
||||
; GCN-NEXT: v_mul_hi_u32 v6, s10, v5
|
||||
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s12, v0
|
||||
; GCN-NEXT: v_mul_lo_u32 v0, s11, v5
|
||||
; GCN-NEXT: v_subb_u32_e32 v3, vcc, v1, v8, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v1, vcc, v6, v4
|
||||
; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
|
||||
; GCN-NEXT: v_mul_lo_u32 v1, s10, v5
|
||||
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s9, v0
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, s11
|
||||
; GCN-NEXT: v_sub_i32_e32 v1, vcc, s8, v1
|
||||
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
|
||||
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc
|
||||
; GCN-NEXT: v_mul_lo_u32 v3, s8, v3
|
||||
; GCN-NEXT: v_mul_hi_u32 v4, s8, v2
|
||||
; GCN-NEXT: v_mul_lo_u32 v5, s9, v2
|
||||
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0
|
||||
; GCN-NEXT: v_mul_lo_u32 v2, s8, v2
|
||||
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
|
||||
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
|
||||
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
|
||||
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s11, v3
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, s9
|
||||
; GCN-NEXT: v_sub_i32_e32 v2, vcc, s10, v2
|
||||
; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
|
||||
; GCN-NEXT: v_subrev_i32_e64 v6, s[0:1], s10, v1
|
||||
; GCN-NEXT: v_subrev_i32_e64 v6, s[0:1], s8, v2
|
||||
; GCN-NEXT: v_subb_u32_e64 v5, s[2:3], v4, v5, s[0:1]
|
||||
; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
|
||||
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v4
|
||||
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
|
||||
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v6
|
||||
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v6
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v4
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v4
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[0:1]
|
||||
; GCN-NEXT: v_subrev_i32_e64 v8, s[0:1], s10, v6
|
||||
; GCN-NEXT: v_subrev_i32_e64 v8, s[0:1], s8, v6
|
||||
; GCN-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]
|
||||
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, s9
|
||||
; GCN-NEXT: v_subb_u32_e32 v0, vcc, v5, v0, vcc
|
||||
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s11, v0
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, s11
|
||||
; GCN-NEXT: v_subb_u32_e32 v3, vcc, v5, v3, vcc
|
||||
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
|
||||
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v1
|
||||
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v2
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
|
||||
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s11, v0
|
||||
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
|
||||
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
|
||||
; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v8, s[0:1]
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
|
||||
; GCN-NEXT: v_xor_b32_e32 v1, s14, v1
|
||||
; GCN-NEXT: v_xor_b32_e32 v4, s14, v0
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, s14
|
||||
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s14, v1
|
||||
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v4, v5, vcc
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
|
||||
; GCN-NEXT: v_xor_b32_e32 v2, s14, v2
|
||||
; GCN-NEXT: v_xor_b32_e32 v3, s14, v3
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, s14
|
||||
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s14, v2
|
||||
; GCN-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
|
||||
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
||||
; GCN-NEXT: s_endpgm
|
||||
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue