forked from OSchip/llvm-project
R600: Fix the fetch limits for R600 generation GPUs
Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64257 llvm-svn: 183560
This commit is contained in:
Tom Stellard
parent
99792774a4
commit
3498e4ff1d
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@ -75,7 +75,16 @@ def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
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"true",
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"Specify use of dedicated vertex cache.">;
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class SubtargetFeatureFetchLimit <string Value> :
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SubtargetFeature <"fetch"#Value,
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"TexVTXClauseSize",
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Value,
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"Limit the maximum number of fetches in a clause to "#Value>;
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def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
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def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
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//===----------------------------------------------------------------------===//
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def AMDGPUInstrInfo : InstrInfo {
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let guessInstructionProperties = 1;
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@ -34,19 +34,10 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
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DefaultSize[1] = 1;
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DefaultSize[2] = 1;
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HasVertexCache = false;
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TexVTXClauseSize = 0;
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ParseSubtargetFeatures(GPU, FS);
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DevName = GPU;
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Device = AMDGPUDeviceInfo::getDeviceFromName(DevName, this, Is64bit);
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// FIXME: The code in the comment below was the original code. But the
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// condition is always true, generating a warning when compiled with
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// gcc. Vincent Lejeune indicated in a mail to llvm-commits 2013-05-23 that he
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// will look into this. The code 'TexVTXClauseSize = 16' is just a temporary
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// equivalent replacement, to get rid of the compiler warning.
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// TexVTXClauseSize = (Device->getGeneration() >= AMDGPUDeviceInfo::HD4XXX)?16:8;
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TexVTXClauseSize = 16;
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}
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AMDGPUSubtarget::~AMDGPUSubtarget() {
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@ -71,7 +71,8 @@ namespace llvm {
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/// These have to be in order with the older generations
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/// having the lower number enumerations.
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enum Generation {
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HD4XXX = 0, ///< 7XX based devices.
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HD3XXX = 0, ///< 6XX based devices.
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HD4XXX, ///< 7XX based devices.
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HD5XXX, ///< Evergreen based devices.
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HD6XXX, ///< NI/Evergreen+ based devices.
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HD7XXX, ///< Southern Islands based devices.
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@ -10,37 +10,39 @@
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class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
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: Processor<Name, itin, Features>;
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def : Proc<"", R600_VLIW5_Itin,
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[FeatureR600ALUInst, FeatureVertexCache]>;
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[FeatureR600ALUInst, FeatureVertexCache, FeatureFetchLimit8]>;
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def : Proc<"r600", R600_VLIW5_Itin,
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[FeatureR600ALUInst , FeatureVertexCache]>;
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[FeatureR600ALUInst , FeatureVertexCache, FeatureFetchLimit8]>;
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def : Proc<"rs880", R600_VLIW5_Itin,
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[FeatureR600ALUInst]>;
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[FeatureR600ALUInst, FeatureFetchLimit8]>;
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def : Proc<"rv670", R600_VLIW5_Itin,
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[FeatureR600ALUInst, FeatureFP64, FeatureVertexCache]>;
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[FeatureR600ALUInst, FeatureFP64, FeatureVertexCache, FeatureFetchLimit8]>;
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def : Proc<"rv710", R600_VLIW5_Itin,
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[FeatureVertexCache]>;
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[FeatureVertexCache, FeatureFetchLimit16]>;
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def : Proc<"rv730", R600_VLIW5_Itin,
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[FeatureVertexCache]>;
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[FeatureVertexCache, FeatureFetchLimit16]>;
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def : Proc<"rv770", R600_VLIW5_Itin,
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[FeatureFP64, FeatureVertexCache]>;
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[FeatureFP64, FeatureVertexCache, FeatureFetchLimit16]>;
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def : Proc<"cedar", R600_VLIW5_Itin,
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[FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
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[FeatureByteAddress, FeatureImages, FeatureVertexCache, FeatureFetchLimit16]>;
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def : Proc<"redwood", R600_VLIW5_Itin,
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[FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
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[FeatureByteAddress, FeatureImages, FeatureVertexCache, FeatureFetchLimit16]>;
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def : Proc<"sumo", R600_VLIW5_Itin,
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[FeatureByteAddress, FeatureImages]>;
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[FeatureByteAddress, FeatureImages, FeatureFetchLimit16]>;
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def : Proc<"juniper", R600_VLIW5_Itin,
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[FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
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[FeatureByteAddress, FeatureImages, FeatureVertexCache, FeatureFetchLimit16]>;
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def : Proc<"cypress", R600_VLIW5_Itin,
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[FeatureByteAddress, FeatureImages, FeatureFP64, FeatureVertexCache]>;
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[FeatureByteAddress, FeatureImages, FeatureFP64, FeatureVertexCache, FeatureFetchLimit16]>;
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def : Proc<"barts", R600_VLIW5_Itin,
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[FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
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[FeatureByteAddress, FeatureImages, FeatureVertexCache, FeatureFetchLimit16]>;
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def : Proc<"turks", R600_VLIW5_Itin,
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[FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
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[FeatureByteAddress, FeatureImages, FeatureVertexCache, FeatureFetchLimit16]>;
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def : Proc<"caicos", R600_VLIW5_Itin,
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[FeatureByteAddress, FeatureImages]>;
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[FeatureByteAddress, FeatureImages, FeatureFetchLimit16]>;
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def : Proc<"cayman", R600_VLIW4_Itin,
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[FeatureByteAddress, FeatureImages, FeatureFP64]>;def : Proc<"SI", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
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[FeatureByteAddress, FeatureImages, FeatureFP64, FeatureFetchLimit16]>;
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def : Proc<"SI", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
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def : Proc<"tahiti", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
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def : Proc<"pitcairn", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
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def : Proc<"verde", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
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@ -0,0 +1,48 @@
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; RUN: llc < %s -march=r600 -mcpu=r600 | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=rs880 | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=rv670 | FileCheck %s
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; R600 supports 8 fetches in a clause
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; CHECK: @fetch_limits_r600
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; CHECK: Fetch clause
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; CHECK: Fetch clause
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define void @fetch_limits_r600() #0 {
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entry:
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%0 = load <4 x float> addrspace(8)* null
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%1 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
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%2 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
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%3 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
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%4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
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%5 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
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%6 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
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%7 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
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%8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
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%res0 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %0, i32 0, i32 0, i32 1)
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%res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1, i32 0, i32 0, i32 1)
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%res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2, i32 0, i32 0, i32 1)
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%res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %3, i32 0, i32 0, i32 1)
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%res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %4, i32 0, i32 0, i32 1)
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%res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %5, i32 0, i32 0, i32 1)
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%res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 0, i32 0, i32 1)
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%res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %7, i32 0, i32 0, i32 1)
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%res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1)
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%a = fadd <4 x float> %res0, %res1
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%b = fadd <4 x float> %res2, %res3
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%c = fadd <4 x float> %res4, %res5
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%d = fadd <4 x float> %res6, %res7
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%e = fadd <4 x float> %res8, %a
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%bc = fadd <4 x float> %b, %c
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%de = fadd <4 x float> %d, %e
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%bcde = fadd <4 x float> %bc, %de
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call void @llvm.R600.store.swizzle(<4 x float> %bcde, i32 0, i32 1)
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ret void
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}
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attributes #0 = { "ShaderType"="0" } ; Pixel Shader
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declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone
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declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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@ -0,0 +1,81 @@
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; RUN: llc < %s -march=r600 -mcpu=rv710 | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=rv730 | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=rv770 | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=cedar | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=sumo | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=juniper | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=cypress | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=barts | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=turks | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=caicos | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s
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; r700+ supports 16 fetches in a clause
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; CHECK: @fetch_limits_r700
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; CHECK: Fetch clause
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; CHECK: Fetch clause
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define void @fetch_limits_r700() #0 {
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entry:
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%0 = load <4 x float> addrspace(8)* null
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%1 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
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%2 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
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%3 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
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%4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
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%5 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
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%6 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
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%7 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
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%8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
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%9 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
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%10 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
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%11 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
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%12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12)
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%13 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13)
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%14 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
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%15 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15)
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%16 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
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%res0 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %0, i32 0, i32 0, i32 1)
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%res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1, i32 0, i32 0, i32 1)
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%res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2, i32 0, i32 0, i32 1)
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%res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %3, i32 0, i32 0, i32 1)
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%res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %4, i32 0, i32 0, i32 1)
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%res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %5, i32 0, i32 0, i32 1)
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%res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 0, i32 0, i32 1)
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%res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %7, i32 0, i32 0, i32 1)
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%res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1)
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%res9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %9, i32 0, i32 0, i32 1)
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%res10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %10, i32 0, i32 0, i32 1)
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%res11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %11, i32 0, i32 0, i32 1)
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%res12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %12, i32 0, i32 0, i32 1)
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%res13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %13, i32 0, i32 0, i32 1)
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%res14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %14, i32 0, i32 0, i32 1)
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%res15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %15, i32 0, i32 0, i32 1)
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%res16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %16, i32 0, i32 0, i32 1)
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%a = fadd <4 x float> %res0, %res1
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%b = fadd <4 x float> %res2, %res3
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%c = fadd <4 x float> %res4, %res5
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%d = fadd <4 x float> %res6, %res7
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%e = fadd <4 x float> %res8, %res9
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%f = fadd <4 x float> %res10, %res11
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%g = fadd <4 x float> %res12, %res13
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%h = fadd <4 x float> %res14, %res15
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%i = fadd <4 x float> %res16, %a
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%bc = fadd <4 x float> %b, %c
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%de = fadd <4 x float> %d, %e
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%fg = fadd <4 x float> %f, %g
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%hi = fadd <4 x float> %h, %i
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%bcde = fadd <4 x float> %bc, %de
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%fghi = fadd <4 x float> %fg, %hi
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%bcdefghi = fadd <4 x float> %bcde, %fghi
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call void @llvm.R600.store.swizzle(<4 x float> %bcdefghi, i32 0, i32 1)
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ret void
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}
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attributes #0 = { "ShaderType"="0" } ; Pixel Shader
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declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone
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declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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