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Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri. 

llvm-svn: 201463
This commit is contained in:
Craig Topper 2014-02-15 07:29:18 +00:00
parent 78bc4d70a1
commit 34875ab0b5
2 changed files with 19 additions and 0 deletions
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10
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -1212,6 +1212,16 @@ def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
"movabs{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, imm:$src)], IIC_MOV>;
}
// Longer forms that use a ModR/M byte. Needed for disassembler
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
"mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
}
} // SchedRW
let SchedRW = [WriteStore] in {

9
llvm/test/MC/Disassembler/X86/x86-32.txt
View File

@ -699,3 +699,12 @@
# CHECK: movl %fs:0, %eax
0x64 0xa1 0x00 0x00 0x00 0x00
# CHECK: movb $-1, %al
0xc6 0xc0 0xff
# CHECK: movw $65535, %ax
0x66 0xc7 0xc0 0xff 0xff
# CHECK: movl $4294967295, %eax
0xc7 0xc0 0xff 0xff 0xff 0xff