forked from OSchip/llvm-project
[X86] Clarify PSHUFB+blend lowering function name. NFC.
Also guard against v32i8 users. llvm-svn: 271024
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@ -9637,11 +9637,13 @@ static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
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return V;
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}
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/// \brief Helper to form a PSHUFB-based shuffle+blend.
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static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
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SDValue V2, ArrayRef<int> Mask,
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SelectionDAG &DAG, bool &V1InUse,
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bool &V2InUse) {
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/// Helper to form a PSHUFB-based shuffle+blend, opportunistically avoiding the
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/// blend if only one input is used.
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static SDValue
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lowerVectorShuffleAsBlendOfPSHUFBs(SDLoc DL, MVT VT, SDValue V1, SDValue V2,
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ArrayRef<int> Mask, SelectionDAG &DAG,
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bool &V1InUse, bool &V2InUse) {
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assert(VT.is128BitVector() && "v32i8 VPSHUFB blend not implemented yet!");
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SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
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SDValue V1Mask[16];
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SDValue V2Mask[16];
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@ -9807,8 +9809,8 @@ static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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// can both shuffle and set up the inefficient blend.
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if (!IsBlendSupported && Subtarget.hasSSSE3()) {
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bool V1InUse, V2InUse;
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return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
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V1InUse, V2InUse);
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return lowerVectorShuffleAsBlendOfPSHUFBs(DL, MVT::v8i16, V1, V2, Mask, DAG,
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V1InUse, V2InUse);
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}
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// We can always bit-blend if we have to so the fallback strategy is to
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@ -10050,8 +10052,8 @@ static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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bool V1InUse = false;
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bool V2InUse = false;
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SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
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DAG, V1InUse, V2InUse);
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SDValue PSHUFB = lowerVectorShuffleAsBlendOfPSHUFBs(
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DL, MVT::v16i8, V1, V2, Mask, DAG, V1InUse, V2InUse);
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// If both V1 and V2 are in use and we can use a direct blend or an unpack,
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// do so. This avoids using them to handle blends-with-zero which is
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