forked from OSchip/llvm-project
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm
was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.
llvm-svn: 86319
This commit is contained in:
Johnny Chen
parent
22053c0f46
commit
3467dcb12d
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@ -377,15 +377,13 @@ multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
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def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
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IIC_iALUr, opc, "\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
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let Inst{4} = 0;
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let Inst{11-4} = 0b00000000;
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let Inst{25} = 0;
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let isCommutable = Commutable;
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}
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def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
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IIC_iALUsr, opc, "\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{25} = 0;
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}
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}
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@ -405,15 +403,13 @@ multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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IIC_iALUr, opc, "s\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
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let isCommutable = Commutable;
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let Inst{4} = 0;
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let Inst{11-4} = 0b00000000;
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let Inst{20} = 1;
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let Inst{25} = 0;
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}
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def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
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IIC_iALUsr, opc, "s\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{20} = 1;
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let Inst{25} = 0;
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}
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@ -435,7 +431,7 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
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def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
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opc, "\t$a, $b",
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[(opnode GPR:$a, GPR:$b)]> {
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let Inst{4} = 0;
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let Inst{11-4} = 0b00000000;
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let Inst{20} = 1;
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let Inst{25} = 0;
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let isCommutable = Commutable;
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@ -443,8 +439,6 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
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def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
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opc, "\t$a, $b",
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[(opnode GPR:$a, so_reg:$b)]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{20} = 1;
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let Inst{25} = 0;
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}
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@ -501,15 +495,13 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
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Requires<[IsARM, CarryDefIsUnused]> {
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let isCommutable = Commutable;
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let Inst{4} = 0;
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let Inst{11-4} = 0b00000000;
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let Inst{25} = 0;
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}
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def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
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Requires<[IsARM, CarryDefIsUnused]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{25} = 0;
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}
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// Carry setting variants
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@ -526,7 +518,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
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Requires<[IsARM, CarryDefIsUsed]> {
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let Defs = [CPSR];
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let Inst{4} = 0;
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let Inst{11-4} = 0b00000000;
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let Inst{20} = 1;
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let Inst{25} = 0;
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}
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@ -535,8 +527,6 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
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Requires<[IsARM, CarryDefIsUsed]> {
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let Defs = [CPSR];
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{20} = 1;
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let Inst{25} = 0;
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}
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@ -963,15 +953,13 @@ def STM : AXI4st<(outs),
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let neverHasSideEffects = 1 in
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def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
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"mov", "\t$dst, $src", []>, UnaryDP {
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let Inst{4} = 0;
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let Inst{11-4} = 0b00000000;
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let Inst{25} = 0;
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}
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def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
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DPSoRegFrm, IIC_iMOVsr,
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"mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{25} = 0;
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}
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@ -1115,8 +1103,6 @@ def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
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def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
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IIC_iALUsr, "rsb", "\t$dst, $a, $b",
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[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{25} = 0;
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}
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@ -1131,8 +1117,6 @@ def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
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def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
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IIC_iALUsr, "rsb", "s\t$dst, $a, $b",
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[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{20} = 1;
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let Inst{25} = 0;
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}
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@ -1149,8 +1133,6 @@ def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
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[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
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Requires<[IsARM, CarryDefIsUnused]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{25} = 0;
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}
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}
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@ -1168,8 +1150,6 @@ def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
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[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
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Requires<[IsARM, CarryDefIsUnused]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{20} = 1;
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let Inst{25} = 0;
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}
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@ -1216,14 +1196,11 @@ def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
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def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
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"mvn", "\t$dst, $src",
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[(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
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let Inst{4} = 0;
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let Inst{11-4} = 0b00000000;
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}
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def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
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IIC_iMOVsr, "mvn", "\t$dst, $src",
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[(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
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let Inst{4} = 1;
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let Inst{7} = 0;
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}
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[(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in
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def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
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IIC_iMOVi, "mvn", "\t$dst, $imm",
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@ -1536,7 +1513,7 @@ def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
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IIC_iCMOVr, "mov", "\t$dst, $true",
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[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
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RegConstraint<"$false = $dst">, UnaryDP {
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let Inst{4} = 0;
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let Inst{11-4} = 0b00000000;
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let Inst{25} = 0;
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}
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@ -1545,8 +1522,6 @@ def MOVCCs : AI1<0b1101, (outs GPR:$dst),
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"mov", "\t$dst, $true",
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[/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
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RegConstraint<"$false = $dst">, UnaryDP {
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{25} = 0;
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}
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