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AMDGPU: Remove redundant patterns for shifts 

llvm-svn: 359895
This commit is contained in:
Matt Arsenault 2019-05-03 15:08:36 +00:00
parent ada33314a2
commit 344d68d3c9
1 changed files with 4 additions and 9 deletions
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13
llvm/lib/Target/AMDGPU/VOP2Instructions.td
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@ -519,11 +519,9 @@ class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
) )
>; >;
let AddedComplexity = 1 in { def : DivergentBinOp<srl, V_LSHRREV_B32_e64>;
def : DivergentBinOp<srl, V_LSHRREV_B32_e64>; def : DivergentBinOp<sra, V_ASHRREV_I32_e64>;
def : DivergentBinOp<sra, V_ASHRREV_I32_e64>; def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;
def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;
}
let SubtargetPredicate = HasAddNoCarryInsts in { let SubtargetPredicate = HasAddNoCarryInsts in {
def : DivergentBinOp<add, V_ADD_U32_e32>; def : DivergentBinOp<add, V_ADD_U32_e32>;
@ -534,12 +532,9 @@ let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] i
def : DivergentBinOp<add, V_ADD_I32_e32>; def : DivergentBinOp<add, V_ADD_I32_e32>;
def : DivergentBinOp<sub, V_SUB_I32_e32>; def : DivergentBinOp<sub, V_SUB_I32_e32>;
def : DivergentBinOp<srl, V_LSHRREV_B32_e32>;
def : DivergentBinOp<sra, V_ASHRREV_I32_e32>;
def : DivergentBinOp<shl, V_LSHLREV_B32_e32>;
}
def : DivergentBinOp<adde, V_ADDC_U32_e32>; def : DivergentBinOp<adde, V_ADDC_U32_e32>;
def : DivergentBinOp<sube, V_SUBB_U32_e32>; def : DivergentBinOp<sube, V_SUBB_U32_e32>;
}
class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> : class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> :
GCNPat< GCNPat<