forked from OSchip/llvm-project
[X86] Update MMX instructions to be tagged with X86SchedWriteWidths types
llvm-svn: 331443
This commit is contained in:
Simon Pilgrim
parent
281919f53f
commit
342ac8cd7e
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@ -109,18 +109,19 @@ multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
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}
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/// PALIGN MMX instructions (require SSSE3).
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multiclass ssse3_palign_mm<string asm, Intrinsic IntId> {
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multiclass ssse3_palign_mm<string asm, Intrinsic IntId,
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X86FoldableSchedWrite sched> {
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def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2, u8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>,
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Sched<[WriteShuffle]>;
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Sched<[sched]>;
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def rmi : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2, u8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>,
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Sched<[WriteShuffleLd, ReadAfterLd]>;
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Sched<[sched.Folded, ReadAfterLd]>;
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}
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multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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@ -285,218 +286,220 @@ let Predicates = [HasMMX] in {
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// Arithmetic Instructions
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defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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// -- Addition
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defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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let Predicates = [HasSSE2] in
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defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w,
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WritePHAdd>;
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SchedWritePHAdd.MMX>;
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defm MMX_PHADDD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,
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WritePHAdd>;
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SchedWritePHAdd.MMX>;
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defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw,
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WritePHAdd>;
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SchedWritePHAdd.MMX>;
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// -- Subtraction
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defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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let Predicates = [HasSSE2] in
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defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w,
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WritePHAdd>;
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SchedWritePHAdd.MMX>;
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defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d,
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WritePHAdd>;
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SchedWritePHAdd.MMX>;
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defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw,
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WritePHAdd>;
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SchedWritePHAdd.MMX>;
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// -- Multiplication
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defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w,
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WriteVecIMul, 1>;
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SchedWriteVecIMul.MMX, 1>;
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defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w,
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WriteVecIMul, 1>;
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SchedWriteVecIMul.MMX, 1>;
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let Predicates = [HasSSE1] in
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defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w,
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WriteVecIMul, 1>;
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SchedWriteVecIMul.MMX, 1>;
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let Predicates = [HasSSE2] in
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defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq,
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WriteVecIMul, 1>;
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SchedWriteVecIMul.MMX, 1>;
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defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw",
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int_x86_ssse3_pmul_hr_sw,
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WriteVecIMul, 1>;
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SchedWriteVecIMul.MMX, 1>;
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// -- Miscellanea
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defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd,
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WriteVecIMul, 1>;
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SchedWriteVecIMul.MMX, 1>;
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defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw",
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int_x86_ssse3_pmadd_ub_sw, WriteVecIMul>;
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int_x86_ssse3_pmadd_ub_sw,
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SchedWriteVecIMul.MMX>;
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let Predicates = [HasSSE1] in {
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defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w,
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WriteVecALU, 1>;
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SchedWriteVecALU.MMX, 1>;
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defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw,
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WritePSADBW, 1>;
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SchedWritePSADBW.MMX, 1>;
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}
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defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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let Constraints = "$src1 = $dst" in
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defm MMX_PALIGNR : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>;
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defm MMX_PALIGNR : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b,
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SchedWriteShuffle.MMX>;
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// Logical Instructions
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defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand,
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WriteVecLogic, 1>;
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SchedWriteVecLogic.MMX, 1>;
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defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por,
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WriteVecLogic, 1>;
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SchedWriteVecLogic.MMX, 1>;
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defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor,
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WriteVecLogic, 1>;
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SchedWriteVecLogic.MMX, 1>;
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defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn,
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WriteVecLogic>;
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SchedWriteVecLogic.MMX>;
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// Shift Instructions
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defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
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int_x86_mmx_psrl_w, int_x86_mmx_psrli_w,
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WriteVecShift>;
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SchedWriteVecShift.MMX>;
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defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
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int_x86_mmx_psrl_d, int_x86_mmx_psrli_d,
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WriteVecShift>;
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SchedWriteVecShift.MMX>;
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defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
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int_x86_mmx_psrl_q, int_x86_mmx_psrli_q,
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WriteVecShift>;
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SchedWriteVecShift.MMX>;
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defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
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int_x86_mmx_psll_w, int_x86_mmx_pslli_w,
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WriteVecShift>;
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SchedWriteVecShift.MMX>;
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defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
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int_x86_mmx_psll_d, int_x86_mmx_pslli_d,
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WriteVecShift>;
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SchedWriteVecShift.MMX>;
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defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
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int_x86_mmx_psll_q, int_x86_mmx_pslli_q,
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WriteVecShift>;
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SchedWriteVecShift.MMX>;
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defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
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int_x86_mmx_psra_w, int_x86_mmx_psrai_w,
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WriteVecShift>;
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SchedWriteVecShift.MMX>;
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defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
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int_x86_mmx_psra_d, int_x86_mmx_psrai_d,
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WriteVecShift>;
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SchedWriteVecShift.MMX>;
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// Comparison Instructions
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defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d,
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WriteVecALU>;
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SchedWriteVecALU.MMX>;
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// -- Unpack Instructions
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defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",
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int_x86_mmx_punpckhbw,
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WriteShuffle>;
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SchedWriteShuffle.MMX>;
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defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",
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int_x86_mmx_punpckhwd,
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WriteShuffle>;
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SchedWriteShuffle.MMX>;
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defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",
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int_x86_mmx_punpckhdq,
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WriteShuffle>;
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SchedWriteShuffle.MMX>;
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defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",
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int_x86_mmx_punpcklbw,
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WriteShuffle,
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SchedWriteShuffle.MMX,
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0, i32mem>;
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defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",
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int_x86_mmx_punpcklwd,
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WriteShuffle,
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SchedWriteShuffle.MMX,
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0, i32mem>;
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defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
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int_x86_mmx_punpckldq,
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WriteShuffle,
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SchedWriteShuffle.MMX,
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0, i32mem>;
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// -- Pack Instructions
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defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb,
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WriteShuffle>;
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SchedWriteShuffle.MMX>;
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defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw,
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WriteShuffle>;
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SchedWriteShuffle.MMX>;
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defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb,
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WriteShuffle>;
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SchedWriteShuffle.MMX>;
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// -- Shuffle Instructions
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defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b,
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WriteVarShuffle>;
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SchedWriteVarShuffle.MMX>;
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def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
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(outs VR64:$dst), (ins VR64:$src1, u8imm:$src2),
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"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR64:$dst,
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(int_x86_sse_pshuf_w VR64:$src1, imm:$src2))]>,
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Sched<[WriteShuffle]>;
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Sched<[SchedWriteShuffle.MMX]>;
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def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
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(outs VR64:$dst), (ins i64mem:$src1, u8imm:$src2),
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"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR64:$dst,
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(int_x86_sse_pshuf_w (load_mmx addr:$src1),
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imm:$src2))]>,
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Sched<[WriteShuffleLd]>;
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Sched<[SchedWriteShuffle.MMX.Folded]>;
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// -- Conversion Instructions
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defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
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@ -570,7 +573,7 @@ def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))),
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(x86mmx (MMX_MOVQ64rm addr:$src))>;
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// Misc.
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||||
let SchedRW = [WriteShuffle] in {
|
||||
let SchedRW = [SchedWriteShuffle.MMX] in {
|
||||
let Uses = [EDI], Predicates = [HasSSE1,Not64BitMode] in
|
||||
def MMX_MASKMOVQ : MMXI32<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
|
||||
"maskmovq\t{$mask, $src|$src, $mask}",
|
||||
|
|
|
|||
|
|
@ -213,6 +213,8 @@ def WriteNop : SchedWrite;
|
|||
// Vector width wrappers.
|
||||
def SchedWriteFAdd
|
||||
: X86SchedWriteWidths<WriteFAdd, WriteFAdd, WriteFAddY, WriteFAddY>;
|
||||
def SchedWriteFHAdd
|
||||
: X86SchedWriteWidths<WriteFHAdd, WriteFHAdd, WriteFHAddY, WriteFHAddY>;
|
||||
def SchedWriteFCmp
|
||||
: X86SchedWriteWidths<WriteFCmp, WriteFCmp, WriteFCmpY, WriteFCmpY>;
|
||||
def SchedWriteFMul
|
||||
|
|
@ -244,6 +246,8 @@ def SchedWriteFVarBlend
|
|||
|
||||
def SchedWriteVecALU
|
||||
: X86SchedWriteWidths<WriteVecALU, WriteVecALU, WriteVecALU, WriteVecALU>;
|
||||
def SchedWritePHAdd
|
||||
: X86SchedWriteWidths<WritePHAdd, WritePHAdd, WritePHAdd, WritePHAdd>;
|
||||
def SchedWriteVecLogic
|
||||
: X86SchedWriteWidths<WriteVecLogic, WriteVecLogic,
|
||||
WriteVecLogicY, WriteVecLogicY>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue