[RISCV] Split RISCV vector builtins into their own file and namespace.

Similar to SVE, this separates the RVV builtlins into their own
region of builtin IDs. Only those IDs are allowed to be used by
the builtin_alias attribute now.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D111923

clang/include/clang/Basic/BuiltinsRISCV.def

@@ -15,8 +15,6 @@
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
-#include "clang/Basic/riscv_vector_builtins.inc"
-
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb,64bit")

clang/include/clang/Basic/BuiltinsRISCVVector.def

@@ -0,0 +1,21 @@
+//==- BuiltinsRISCVVector.def - RISC-V Vector Builtin Database ---*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the RISC-V-specific builtin function database.  Users of
+// this file must define the BUILTIN macro to make use of this information.
+//
+//===----------------------------------------------------------------------===//
+
+#if defined(BUILTIN) && !defined(TARGET_BUILTIN)
+#   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
+#endif
+
+#include "clang/Basic/riscv_vector_builtins.inc"
+
+#undef BUILTIN
+#undef TARGET_BUILTIN

clang/include/clang/Basic/TargetBuiltins.h

@@ -124,10 +124,21 @@ namespace clang {
   enum { LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1, LastTSBuiltin };
   }
 
+  namespace RISCVVector {
+  enum {
+    LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1,
+#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
+#include "clang/Basic/BuiltinsRISCVVector.def"
+    FirstTSBuiltin,
+  };
+  }
+
   /// RISCV builtins
   namespace RISCV {
   enum {
     LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1,
+    FirstRVVBuiltin = clang::Builtin::FirstTSBuiltin,
+    LastRVVBuiltin = RISCVVector::FirstTSBuiltin - 1,
 #define BUILTIN(ID, TYPE, ATTRS) BI##ID,
 #include "clang/Basic/BuiltinsRISCV.def"
     LastTSBuiltin

clang/include/clang/module.modulemap

@@ -45,6 +45,7 @@ module Clang_Basic {
   textual header "Basic/BuiltinsNVPTX.def"
   textual header "Basic/BuiltinsPPC.def"
   textual header "Basic/BuiltinsRISCV.def"
+  textual header "Basic/BuiltinsRISCVVector.def"
   textual header "Basic/BuiltinsSVE.def"
   textual header "Basic/BuiltinsSystemZ.def"
   textual header "Basic/BuiltinsWebAssembly.def"

clang/lib/Basic/Targets/RISCV.cpp

@@ -184,6 +184,11 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
 }
 
 const Builtin::Info RISCVTargetInfo::BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)                                               \
+  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
+    {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
+#include "clang/Basic/BuiltinsRISCVVector.def"
 #define BUILTIN(ID, TYPE, ATTRS)                                               \
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \

clang/lib/Sema/SemaChecking.cpp

@@ -3661,137 +3661,137 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
     return true;
 
   switch (BuiltinID) {
-  case RISCV::BI__builtin_rvv_vsetvli:
+  case RISCVVector::BI__builtin_rvv_vsetvli:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3) ||
            CheckRISCVLMUL(TheCall, 2);
-  case RISCV::BI__builtin_rvv_vsetvlimax:
+  case RISCVVector::BI__builtin_rvv_vsetvlimax:
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
            CheckRISCVLMUL(TheCall, 1);
-  case RISCV::BI__builtin_rvv_vget_v_i8m2_i8m1:
-  case RISCV::BI__builtin_rvv_vget_v_i16m2_i16m1:
-  case RISCV::BI__builtin_rvv_vget_v_i32m2_i32m1:
-  case RISCV::BI__builtin_rvv_vget_v_i64m2_i64m1:
-  case RISCV::BI__builtin_rvv_vget_v_f32m2_f32m1:
-  case RISCV::BI__builtin_rvv_vget_v_f64m2_f64m1:
-  case RISCV::BI__builtin_rvv_vget_v_u8m2_u8m1:
-  case RISCV::BI__builtin_rvv_vget_v_u16m2_u16m1:
-  case RISCV::BI__builtin_rvv_vget_v_u32m2_u32m1:
-  case RISCV::BI__builtin_rvv_vget_v_u64m2_u64m1:
-  case RISCV::BI__builtin_rvv_vget_v_i8m4_i8m2:
-  case RISCV::BI__builtin_rvv_vget_v_i16m4_i16m2:
-  case RISCV::BI__builtin_rvv_vget_v_i32m4_i32m2:
-  case RISCV::BI__builtin_rvv_vget_v_i64m4_i64m2:
-  case RISCV::BI__builtin_rvv_vget_v_f32m4_f32m2:
-  case RISCV::BI__builtin_rvv_vget_v_f64m4_f64m2:
-  case RISCV::BI__builtin_rvv_vget_v_u8m4_u8m2:
-  case RISCV::BI__builtin_rvv_vget_v_u16m4_u16m2:
-  case RISCV::BI__builtin_rvv_vget_v_u32m4_u32m2:
-  case RISCV::BI__builtin_rvv_vget_v_u64m4_u64m2:
-  case RISCV::BI__builtin_rvv_vget_v_i8m8_i8m4:
-  case RISCV::BI__builtin_rvv_vget_v_i16m8_i16m4:
-  case RISCV::BI__builtin_rvv_vget_v_i32m8_i32m4:
-  case RISCV::BI__builtin_rvv_vget_v_i64m8_i64m4:
-  case RISCV::BI__builtin_rvv_vget_v_f32m8_f32m4:
-  case RISCV::BI__builtin_rvv_vget_v_f64m8_f64m4:
-  case RISCV::BI__builtin_rvv_vget_v_u8m8_u8m4:
-  case RISCV::BI__builtin_rvv_vget_v_u16m8_u16m4:
-  case RISCV::BI__builtin_rvv_vget_v_u32m8_u32m4:
-  case RISCV::BI__builtin_rvv_vget_v_u64m8_u64m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_i8m2_i8m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i16m2_i16m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i32m2_i32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i64m2_i64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_f32m2_f32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_f64m2_f64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u8m2_u8m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u16m2_u16m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u32m2_u32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u64m2_u64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i8m4_i8m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i16m4_i16m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i32m4_i32m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i64m4_i64m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_f32m4_f32m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_f64m4_f64m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u8m4_u8m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u16m4_u16m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u32m4_u32m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u64m4_u64m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i8m8_i8m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_i16m8_i16m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_i32m8_i32m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_i64m8_i64m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_f32m8_f32m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_f64m8_f64m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_u8m8_u8m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_u16m8_u16m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_u32m8_u32m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_u64m8_u64m4:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
-  case RISCV::BI__builtin_rvv_vget_v_i8m4_i8m1:
-  case RISCV::BI__builtin_rvv_vget_v_i16m4_i16m1:
-  case RISCV::BI__builtin_rvv_vget_v_i32m4_i32m1:
-  case RISCV::BI__builtin_rvv_vget_v_i64m4_i64m1:
-  case RISCV::BI__builtin_rvv_vget_v_f32m4_f32m1:
-  case RISCV::BI__builtin_rvv_vget_v_f64m4_f64m1:
-  case RISCV::BI__builtin_rvv_vget_v_u8m4_u8m1:
-  case RISCV::BI__builtin_rvv_vget_v_u16m4_u16m1:
-  case RISCV::BI__builtin_rvv_vget_v_u32m4_u32m1:
-  case RISCV::BI__builtin_rvv_vget_v_u64m4_u64m1:
-  case RISCV::BI__builtin_rvv_vget_v_i8m8_i8m2:
-  case RISCV::BI__builtin_rvv_vget_v_i16m8_i16m2:
-  case RISCV::BI__builtin_rvv_vget_v_i32m8_i32m2:
-  case RISCV::BI__builtin_rvv_vget_v_i64m8_i64m2:
-  case RISCV::BI__builtin_rvv_vget_v_f32m8_f32m2:
-  case RISCV::BI__builtin_rvv_vget_v_f64m8_f64m2:
-  case RISCV::BI__builtin_rvv_vget_v_u8m8_u8m2:
-  case RISCV::BI__builtin_rvv_vget_v_u16m8_u16m2:
-  case RISCV::BI__builtin_rvv_vget_v_u32m8_u32m2:
-  case RISCV::BI__builtin_rvv_vget_v_u64m8_u64m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i8m4_i8m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i16m4_i16m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i32m4_i32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i64m4_i64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_f32m4_f32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_f64m4_f64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u8m4_u8m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u16m4_u16m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u32m4_u32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u64m4_u64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i8m8_i8m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i16m8_i16m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i32m8_i32m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i64m8_i64m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_f32m8_f32m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_f64m8_f64m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u8m8_u8m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u16m8_u16m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u32m8_u32m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u64m8_u64m2:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
-  case RISCV::BI__builtin_rvv_vget_v_i8m8_i8m1:
-  case RISCV::BI__builtin_rvv_vget_v_i16m8_i16m1:
-  case RISCV::BI__builtin_rvv_vget_v_i32m8_i32m1:
-  case RISCV::BI__builtin_rvv_vget_v_i64m8_i64m1:
-  case RISCV::BI__builtin_rvv_vget_v_f32m8_f32m1:
-  case RISCV::BI__builtin_rvv_vget_v_f64m8_f64m1:
-  case RISCV::BI__builtin_rvv_vget_v_u8m8_u8m1:
-  case RISCV::BI__builtin_rvv_vget_v_u16m8_u16m1:
-  case RISCV::BI__builtin_rvv_vget_v_u32m8_u32m1:
-  case RISCV::BI__builtin_rvv_vget_v_u64m8_u64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i8m8_i8m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i16m8_i16m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i32m8_i32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i64m8_i64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_f32m8_f32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_f64m8_f64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u8m8_u8m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u16m8_u16m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u32m8_u32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u64m8_u64m1:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 7);
-  case RISCV::BI__builtin_rvv_vset_v_i8m1_i8m2:
-  case RISCV::BI__builtin_rvv_vset_v_i16m1_i16m2:
-  case RISCV::BI__builtin_rvv_vset_v_i32m1_i32m2:
-  case RISCV::BI__builtin_rvv_vset_v_i64m1_i64m2:
-  case RISCV::BI__builtin_rvv_vset_v_f32m1_f32m2:
-  case RISCV::BI__builtin_rvv_vset_v_f64m1_f64m2:
-  case RISCV::BI__builtin_rvv_vset_v_u8m1_u8m2:
-  case RISCV::BI__builtin_rvv_vset_v_u16m1_u16m2:
-  case RISCV::BI__builtin_rvv_vset_v_u32m1_u32m2:
-  case RISCV::BI__builtin_rvv_vset_v_u64m1_u64m2:
-  case RISCV::BI__builtin_rvv_vset_v_i8m2_i8m4:
-  case RISCV::BI__builtin_rvv_vset_v_i16m2_i16m4:
-  case RISCV::BI__builtin_rvv_vset_v_i32m2_i32m4:
-  case RISCV::BI__builtin_rvv_vset_v_i64m2_i64m4:
-  case RISCV::BI__builtin_rvv_vset_v_f32m2_f32m4:
-  case RISCV::BI__builtin_rvv_vset_v_f64m2_f64m4:
-  case RISCV::BI__builtin_rvv_vset_v_u8m2_u8m4:
-  case RISCV::BI__builtin_rvv_vset_v_u16m2_u16m4:
-  case RISCV::BI__builtin_rvv_vset_v_u32m2_u32m4:
-  case RISCV::BI__builtin_rvv_vset_v_u64m2_u64m4:
-  case RISCV::BI__builtin_rvv_vset_v_i8m4_i8m8:
-  case RISCV::BI__builtin_rvv_vset_v_i16m4_i16m8:
-  case RISCV::BI__builtin_rvv_vset_v_i32m4_i32m8:
-  case RISCV::BI__builtin_rvv_vset_v_i64m4_i64m8:
-  case RISCV::BI__builtin_rvv_vset_v_f32m4_f32m8:
-  case RISCV::BI__builtin_rvv_vset_v_f64m4_f64m8:
-  case RISCV::BI__builtin_rvv_vset_v_u8m4_u8m8:
-  case RISCV::BI__builtin_rvv_vset_v_u16m4_u16m8:
-  case RISCV::BI__builtin_rvv_vset_v_u32m4_u32m8:
-  case RISCV::BI__builtin_rvv_vset_v_u64m4_u64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i8m1_i8m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_i16m1_i16m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_i32m1_i32m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_i64m1_i64m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_f32m1_f32m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_f64m1_f64m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_u8m1_u8m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_u16m1_u16m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_u32m1_u32m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_u64m1_u64m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_i8m2_i8m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i16m2_i16m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i32m2_i32m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i64m2_i64m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_f32m2_f32m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_f64m2_f64m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u8m2_u8m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u16m2_u16m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u32m2_u32m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u64m2_u64m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i8m4_i8m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i16m4_i16m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i32m4_i32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i64m4_i64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_f32m4_f32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_f64m4_f64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u8m4_u8m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u16m4_u16m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u32m4_u32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u64m4_u64m8:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
-  case RISCV::BI__builtin_rvv_vset_v_i8m1_i8m4:
-  case RISCV::BI__builtin_rvv_vset_v_i16m1_i16m4:
-  case RISCV::BI__builtin_rvv_vset_v_i32m1_i32m4:
-  case RISCV::BI__builtin_rvv_vset_v_i64m1_i64m4:
-  case RISCV::BI__builtin_rvv_vset_v_f32m1_f32m4:
-  case RISCV::BI__builtin_rvv_vset_v_f64m1_f64m4:
-  case RISCV::BI__builtin_rvv_vset_v_u8m1_u8m4:
-  case RISCV::BI__builtin_rvv_vset_v_u16m1_u16m4:
-  case RISCV::BI__builtin_rvv_vset_v_u32m1_u32m4:
-  case RISCV::BI__builtin_rvv_vset_v_u64m1_u64m4:
-  case RISCV::BI__builtin_rvv_vset_v_i8m2_i8m8:
-  case RISCV::BI__builtin_rvv_vset_v_i16m2_i16m8:
-  case RISCV::BI__builtin_rvv_vset_v_i32m2_i32m8:
-  case RISCV::BI__builtin_rvv_vset_v_i64m2_i64m8:
-  case RISCV::BI__builtin_rvv_vset_v_f32m2_f32m8:
-  case RISCV::BI__builtin_rvv_vset_v_f64m2_f64m8:
-  case RISCV::BI__builtin_rvv_vset_v_u8m2_u8m8:
-  case RISCV::BI__builtin_rvv_vset_v_u16m2_u16m8:
-  case RISCV::BI__builtin_rvv_vset_v_u32m2_u32m8:
-  case RISCV::BI__builtin_rvv_vset_v_u64m2_u64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i8m1_i8m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i16m1_i16m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i32m1_i32m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i64m1_i64m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_f32m1_f32m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_f64m1_f64m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u8m1_u8m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u16m1_u16m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u32m1_u32m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u64m1_u64m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i8m2_i8m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i16m2_i16m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i32m2_i32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i64m2_i64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_f32m2_f32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_f64m2_f64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u8m2_u8m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u16m2_u16m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u32m2_u32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u64m2_u64m8:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
-  case RISCV::BI__builtin_rvv_vset_v_i8m1_i8m8:
-  case RISCV::BI__builtin_rvv_vset_v_i16m1_i16m8:
-  case RISCV::BI__builtin_rvv_vset_v_i32m1_i32m8:
-  case RISCV::BI__builtin_rvv_vset_v_i64m1_i64m8:
-  case RISCV::BI__builtin_rvv_vset_v_f32m1_f32m8:
-  case RISCV::BI__builtin_rvv_vset_v_f64m1_f64m8:
-  case RISCV::BI__builtin_rvv_vset_v_u8m1_u8m8:
-  case RISCV::BI__builtin_rvv_vset_v_u16m1_u16m8:
-  case RISCV::BI__builtin_rvv_vset_v_u32m1_u32m8:
-  case RISCV::BI__builtin_rvv_vset_v_u64m1_u64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i8m1_i8m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i16m1_i16m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i32m1_i32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i64m1_i64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_f32m1_f32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_f64m1_f64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u8m1_u8m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u16m1_u16m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u32m1_u32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u64m1_u64m8:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 7);
   }
 

clang/lib/Sema/SemaDeclAttr.cpp

@@ -5340,8 +5340,8 @@ static void handleArmBuiltinAliasAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
 }
 
 static bool RISCVAliasValid(unsigned BuiltinID, StringRef AliasName) {
-  return BuiltinID >= Builtin::FirstTSBuiltin &&
-         BuiltinID < RISCV::LastTSBuiltin;
+  return BuiltinID >= RISCV::FirstRVVBuiltin &&
+         BuiltinID <= RISCV::LastRVVBuiltin;
 }
 
 static void handleBuiltinAliasAttr(Sema &S, Decl *D,

clang/utils/TableGen/RISCVVEmitter.cpp

@@ -1046,7 +1046,7 @@ void RVVEmitter::createCodeGen(raw_ostream &OS) {
       PrevDef->emitCodeGenSwitchBody(OS);
     }
     PrevDef = Def.get();
-    OS << "case RISCV::BI__builtin_rvv_" << Def->getName() << ":\n";
+    OS << "case RISCVVector::BI__builtin_rvv_" << Def->getName() << ":\n";
   }
   Defs.back()->emitCodeGenSwitchBody(OS);
   OS << "\n";