forked from OSchip/llvm-project
[SDAG] match rotate pattern with extra 'or' operation
This is another fold generalized from D111530.
We can find a common source for a rotate operation hidden inside an 'or':
https://alive2.llvm.org/ce/z/9pV8hn
Deciding when this is profitable vs. a funnel-shift is tricky, but this
does not show any regressions: if a target has a rotate but it does not
have a funnel-shift, then try to form the rotate here. That is why we
don't have x86 test diffs for the scalar tests that are duplicated from
AArch64 ( 74a65e3834 ) - shld/shrd are available. That also makes it
difficult to show vector diffs - the only case where I found a diff was
on x86 AVX512 or XOP with i64 elements.
There's an additional check for a legal type to avoid a problem seen
with x86-32 where we form a 64-bit rotate but then it gets split
inefficiently. We might avoid that by adding more rotate folds, but
I didn't check to see what is missing on that path.
This gets most of the motivating patterns for AArch64 / ARM that are in
D111530.
We still need a couple of enhancements to setcc pattern matching with
rotate/funnel-shift to get the rest.
Differential Revision: https://reviews.llvm.org/D120933
This commit is contained in:
Sanjay Patel
parent
0f20a35b9e
commit
341623653d
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@ -7405,11 +7405,6 @@ SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
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if (LHSShift.getOpcode() == RHSShift.getOpcode())
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return SDValue(); // Shifts must disagree.
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// TODO: Support pre-legalization funnel-shift by constant.
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bool IsRotate = LHSShift.getOperand(0) == RHSShift.getOperand(0);
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if (!IsRotate && !(HasFSHL || HasFSHR))
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return SDValue(); // Requires funnel shift support.
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// Canonicalize shl to left side in a shl/srl pair.
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if (RHSShift.getOpcode() == ISD::SHL) {
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std::swap(LHS, RHS);
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@ -7423,15 +7418,57 @@ SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
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SDValue RHSShiftArg = RHSShift.getOperand(0);
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SDValue RHSShiftAmt = RHSShift.getOperand(1);
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auto MatchRotateSum = [EltSizeInBits](ConstantSDNode *LHS,
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ConstantSDNode *RHS) {
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return (LHS->getAPIntValue() + RHS->getAPIntValue()) == EltSizeInBits;
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};
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// TODO: Support pre-legalization funnel-shift by constant.
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bool IsRotate = LHSShift.getOperand(0) == RHSShift.getOperand(0);
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if (!IsRotate && !(HasFSHL || HasFSHR)) {
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if (TLI.isTypeLegal(VT) && LHS.hasOneUse() && RHS.hasOneUse() &&
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ISD::matchBinaryPredicate(LHSShiftAmt, RHSShiftAmt, MatchRotateSum)) {
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// Look for a disguised rotate by constant.
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// The common shifted operand X may be hidden inside another 'or'.
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SDValue X, Y;
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auto matchOr = [&X, &Y](SDValue Or, SDValue CommonOp) {
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if (!Or.hasOneUse() || Or.getOpcode() != ISD::OR)
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return false;
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if (CommonOp == Or.getOperand(0)) {
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X = CommonOp;
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Y = Or.getOperand(1);
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return true;
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}
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if (CommonOp == Or.getOperand(1)) {
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X = CommonOp;
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Y = Or.getOperand(0);
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return true;
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}
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return false;
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};
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// (shl (X | Y), C1) | (srl X, C2) --> (rotl X, C1) | (shl Y, C1)
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if (matchOr(LHSShiftArg, RHSShiftArg)) {
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SDValue RotX = DAG.getNode(ISD::ROTL, DL, VT, X, LHSShiftAmt);
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SDValue ShlY = DAG.getNode(ISD::SHL, DL, VT, Y, LHSShiftAmt);
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return DAG.getNode(ISD::OR, DL, VT, RotX, ShlY);
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}
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// (shl X, C1) | (srl (X | Y), C2) --> (rotl X, C1) | (srl Y, C2)
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if (matchOr(RHSShiftArg, LHSShiftArg)) {
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SDValue RotX = DAG.getNode(ISD::ROTL, DL, VT, X, LHSShiftAmt);
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SDValue SrlY = DAG.getNode(ISD::SRL, DL, VT, Y, RHSShiftAmt);
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return DAG.getNode(ISD::OR, DL, VT, RotX, SrlY);
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}
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}
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return SDValue(); // Requires funnel shift support.
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}
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// fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
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// fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
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// fold (or (shl x, C1), (srl y, C2)) -> (fshl x, y, C1)
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// fold (or (shl x, C1), (srl y, C2)) -> (fshr x, y, C2)
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// iff C1+C2 == EltSizeInBits
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auto MatchRotateSum = [EltSizeInBits](ConstantSDNode *LHS,
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ConstantSDNode *RHS) {
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return (LHS->getAPIntValue() + RHS->getAPIntValue()) == EltSizeInBits;
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};
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if (ISD::matchBinaryPredicate(LHSShiftAmt, RHSShiftAmt, MatchRotateSum)) {
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SDValue Res;
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if (IsRotate && (HasROTL || HasROTR || !(HasFSHL || HasFSHR))) {
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@ -12,8 +12,7 @@ define i128 @opt_setcc_lt_power_of_2(i128 %a) nounwind {
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: adds x0, x0, #1
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; CHECK-NEXT: adcs x1, x1, xzr
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; CHECK-NEXT: orr x8, x0, x1
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; CHECK-NEXT: extr x8, x1, x8, #60
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; CHECK-NEXT: orr x8, x1, x0, lsr #60
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; CHECK-NEXT: cbnz x8, .LBB0_1
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; CHECK-NEXT: // %bb.2: // %exit
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; CHECK-NEXT: ret
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@ -32,8 +31,7 @@ exit:
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define i1 @opt_setcc_srl_eq_zero(i128 %a) nounwind {
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; CHECK-LABEL: opt_setcc_srl_eq_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr x8, x0, x1
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; CHECK-NEXT: extr x8, x1, x8, #17
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; CHECK-NEXT: orr x8, x1, x0, lsr #17
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; CHECK-NEXT: cmp x8, #0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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@ -45,8 +43,7 @@ define i1 @opt_setcc_srl_eq_zero(i128 %a) nounwind {
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define i1 @opt_setcc_srl_ne_zero(i128 %a) nounwind {
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; CHECK-LABEL: opt_setcc_srl_ne_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr x8, x0, x1
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; CHECK-NEXT: extr x8, x1, x8, #17
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; CHECK-NEXT: orr x8, x1, x0, lsr #17
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; CHECK-NEXT: cmp x8, #0
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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@ -58,8 +55,7 @@ define i1 @opt_setcc_srl_ne_zero(i128 %a) nounwind {
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define i1 @opt_setcc_shl_eq_zero(i128 %a) nounwind {
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; CHECK-LABEL: opt_setcc_shl_eq_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr x8, x1, x0
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; CHECK-NEXT: extr x8, x8, x0, #47
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; CHECK-NEXT: orr x8, x0, x1, lsl #17
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; CHECK-NEXT: cmp x8, #0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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@ -71,8 +67,7 @@ define i1 @opt_setcc_shl_eq_zero(i128 %a) nounwind {
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define i1 @opt_setcc_shl_ne_zero(i128 %a) nounwind {
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; CHECK-LABEL: opt_setcc_shl_ne_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr x8, x1, x0
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; CHECK-NEXT: extr x8, x8, x0, #47
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; CHECK-NEXT: orr x8, x0, x1, lsl #17
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; CHECK-NEXT: cmp x8, #0
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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@ -106,8 +101,7 @@ define i1 @opt_setcc_shl_eq_zero_multiple_shl_users(i128 %a) nounwind {
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define i1 @opt_setcc_expanded_shl_correct_shifts(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: opt_setcc_expanded_shl_correct_shifts:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr x8, x0, x1
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; CHECK-NEXT: extr x8, x8, x1, #47
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; CHECK-NEXT: orr x8, x1, x0, lsl #17
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; CHECK-NEXT: cmp x8, #0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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@ -690,8 +690,8 @@ define i64 @mix_logic_shl(i64 %x0, i64 %x1, i64 %y, i64 %z) {
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define i32 @or_fshl_commute0(i32 %x, i32 %y) {
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; CHECK-LABEL: or_fshl_commute0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w8, w0, w1
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; CHECK-NEXT: extr w0, w8, w0, #27
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; CHECK-NEXT: ror w8, w0, #27
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; CHECK-NEXT: orr w0, w8, w1, lsl #5
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; CHECK-NEXT: ret
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%or1 = or i32 %x, %y
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%sh1 = shl i32 %or1, 5
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@ -703,8 +703,8 @@ define i32 @or_fshl_commute0(i32 %x, i32 %y) {
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define i64 @or_fshl_commute1(i64 %x, i64 %y) {
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; CHECK-LABEL: or_fshl_commute1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w8, w1, w0
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; CHECK-NEXT: extr x0, x8, x0, #29
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; CHECK-NEXT: ror x8, x0, #29
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; CHECK-NEXT: orr x0, x8, x1, lsl #35
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; CHECK-NEXT: ret
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%or1 = or i64 %y, %x
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%sh1 = shl i64 %or1, 35
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@ -762,8 +762,8 @@ define i32 @or_fshl_wrong_shift(i32 %x, i32 %y) {
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define i64 @or_fshr_commute0(i64 %x, i64 %y) {
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; CHECK-LABEL: or_fshr_commute0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr x8, x0, x1
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; CHECK-NEXT: extr x0, x0, x8, #24
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; CHECK-NEXT: ror x8, x0, #24
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; CHECK-NEXT: orr x0, x8, x1, lsr #24
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; CHECK-NEXT: ret
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%or1 = or i64 %x, %y
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%sh1 = shl i64 %x, 40
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@ -775,8 +775,8 @@ define i64 @or_fshr_commute0(i64 %x, i64 %y) {
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define i32 @or_fshr_commute1(i32 %x, i32 %y) {
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; CHECK-LABEL: or_fshr_commute1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w8, w1, w0
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; CHECK-NEXT: extr w0, w0, w8, #29
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; CHECK-NEXT: ror w8, w0, #29
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; CHECK-NEXT: orr w0, w8, w1, lsr #29
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; CHECK-NEXT: ret
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%or1 = or i32 %y, %x
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%sh1 = shl i32 %x, 3
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@ -630,14 +630,10 @@ define i32 @icmp64_uge_m2(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
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; CHECKV7M-NEXT: ldrd lr, r0, [sp, #8]
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; CHECKV7M-NEXT: beq .LBB6_2
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; CHECKV7M-NEXT: @ %bb.1: @ %then
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; CHECKV7M-NEXT: orrs r2, r3
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; CHECKV7M-NEXT: lsrs r2, r2, #17
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; CHECKV7M-NEXT: orr.w r2, r2, r3, lsl #15
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; CHECKV7M-NEXT: orr.w r3, r12, r1
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; CHECKV7M-NEXT: orr.w r2, r3, r2, lsr #17
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; CHECKV7M-NEXT: orr.w r1, r1, r12, lsr #17
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; CHECKV7M-NEXT: cmp r2, #0
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; CHECKV7M-NEXT: mov r2, r0
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; CHECKV7M-NEXT: lsr.w r3, r3, #17
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; CHECKV7M-NEXT: orr.w r1, r3, r1, lsl #15
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; CHECKV7M-NEXT: it ne
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; CHECKV7M-NEXT: movne r2, lr
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; CHECKV7M-NEXT: cmp r1, #0
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@ -646,9 +642,7 @@ define i32 @icmp64_uge_m2(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
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; CHECKV7M-NEXT: add r0, r2
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; CHECKV7M-NEXT: pop {r7, pc}
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; CHECKV7M-NEXT: .LBB6_2: @ %else
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; CHECKV7M-NEXT: orr.w r1, r2, r3
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; CHECKV7M-NEXT: lsrs r1, r1, #17
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; CHECKV7M-NEXT: orr.w r1, r1, r3, lsl #15
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; CHECKV7M-NEXT: orr.w r1, r3, r2, lsr #17
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; CHECKV7M-NEXT: cmp r1, #0
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; CHECKV7M-NEXT: it ne
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; CHECKV7M-NEXT: movne r0, lr
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@ -664,14 +658,10 @@ define i32 @icmp64_uge_m2(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
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; CHECKV7A-NEXT: lsls r4, r4, #31
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; CHECKV7A-NEXT: beq .LBB6_2
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; CHECKV7A-NEXT: @ %bb.1: @ %then
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; CHECKV7A-NEXT: orrs r2, r3
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; CHECKV7A-NEXT: lsrs r2, r2, #17
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; CHECKV7A-NEXT: orr.w r2, r2, r3, lsl #15
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; CHECKV7A-NEXT: orr.w r3, r12, r1
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; CHECKV7A-NEXT: orr.w r2, r3, r2, lsr #17
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; CHECKV7A-NEXT: orr.w r1, r1, r12, lsr #17
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; CHECKV7A-NEXT: cmp r2, #0
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; CHECKV7A-NEXT: mov r2, r0
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; CHECKV7A-NEXT: lsr.w r3, r3, #17
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; CHECKV7A-NEXT: orr.w r1, r3, r1, lsl #15
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; CHECKV7A-NEXT: it ne
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; CHECKV7A-NEXT: movne r2, lr
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; CHECKV7A-NEXT: cmp r1, #0
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@ -680,9 +670,7 @@ define i32 @icmp64_uge_m2(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
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; CHECKV7A-NEXT: add r0, r2
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; CHECKV7A-NEXT: pop {r4, pc}
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; CHECKV7A-NEXT: .LBB6_2: @ %else
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; CHECKV7A-NEXT: orr.w r1, r2, r3
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; CHECKV7A-NEXT: lsrs r1, r1, #17
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; CHECKV7A-NEXT: orr.w r1, r1, r3, lsl #15
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; CHECKV7A-NEXT: orr.w r1, r3, r2, lsr #17
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; CHECKV7A-NEXT: cmp r1, #0
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; CHECKV7A-NEXT: it ne
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; CHECKV7A-NEXT: movne r0, lr
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@ -12,9 +12,7 @@ define i64 @opt_setcc_lt_power_of_2(i64 %a) nounwind {
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: adds r0, r0, #1
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; CHECK-NEXT: adc r1, r1, #0
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; CHECK-NEXT: orr r2, r0, r1
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; CHECK-NEXT: uxth r3, r1
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; CHECK-NEXT: orr r2, r3, r2, lsr #16
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; CHECK-NEXT: orr r2, r1, r0, lsr #16
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: bne .LBB0_1
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; CHECK-NEXT: @ %bb.2: @ %exit
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@ -34,9 +32,7 @@ exit:
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define i1 @opt_setcc_srl_eq_zero(i64 %a) nounwind {
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; CHECK-LABEL: opt_setcc_srl_eq_zero:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: orr r0, r0, r1
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; CHECK-NEXT: lsr r0, r0, #17
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; CHECK-NEXT: orr r0, r0, r1, lsl #15
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; CHECK-NEXT: orr r0, r1, r0, lsr #17
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; CHECK-NEXT: clz r0, r0
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; CHECK-NEXT: lsr r0, r0, #5
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; CHECK-NEXT: bx lr
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@ -48,9 +44,7 @@ define i1 @opt_setcc_srl_eq_zero(i64 %a) nounwind {
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define i1 @opt_setcc_srl_ne_zero(i64 %a) nounwind {
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; CHECK-LABEL: opt_setcc_srl_ne_zero:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: orr r0, r0, r1
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; CHECK-NEXT: lsr r0, r0, #17
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; CHECK-NEXT: orr r0, r0, r1, lsl #15
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; CHECK-NEXT: orr r0, r1, r0, lsr #17
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: movwne r0, #1
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; CHECK-NEXT: bx lr
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@ -62,9 +56,7 @@ define i1 @opt_setcc_srl_ne_zero(i64 %a) nounwind {
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define i1 @opt_setcc_shl_eq_zero(i64 %a) nounwind {
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; CHECK-LABEL: opt_setcc_shl_eq_zero:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: orr r1, r1, r0
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; CHECK-NEXT: lsl r1, r1, #17
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; CHECK-NEXT: orr r0, r1, r0, lsr #15
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; CHECK-NEXT: orr r0, r0, r1, lsl #17
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; CHECK-NEXT: clz r0, r0
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; CHECK-NEXT: lsr r0, r0, #5
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; CHECK-NEXT: bx lr
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@ -76,9 +68,7 @@ define i1 @opt_setcc_shl_eq_zero(i64 %a) nounwind {
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define i1 @opt_setcc_shl_ne_zero(i64 %a) nounwind {
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; CHECK-LABEL: opt_setcc_shl_ne_zero:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: orr r1, r1, r0
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; CHECK-NEXT: lsl r1, r1, #17
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; CHECK-NEXT: orr r0, r1, r0, lsr #15
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; CHECK-NEXT: orr r0, r0, r1, lsl #17
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: movwne r0, #1
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; CHECK-NEXT: bx lr
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@ -113,9 +103,7 @@ define i1 @opt_setcc_shl_eq_zero_multiple_shl_users(i64 %a) nounwind {
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define i1 @opt_setcc_expanded_shl_correct_shifts(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: opt_setcc_expanded_shl_correct_shifts:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: orr r0, r0, r1
|
||||
; CHECK-NEXT: lsl r0, r0, #17
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsr #15
|
||||
; CHECK-NEXT: orr r0, r1, r0, lsl #17
|
||||
; CHECK-NEXT: clz r0, r0
|
||||
; CHECK-NEXT: lsr r0, r0, #5
|
||||
; CHECK-NEXT: bx lr
|
||||
|
|
|
|||
|
|
@ -230,13 +230,19 @@ define <4 x i32> @or_fshl_v4i32(<4 x i32> %x, <4 x i32> %y) {
|
|||
}
|
||||
|
||||
define <2 x i64> @or_fshr_v2i64(<2 x i64> %x, <2 x i64> %y) {
|
||||
; CHECK-LABEL: or_fshr_v2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vpor %xmm1, %xmm0, %xmm1
|
||||
; CHECK-NEXT: vpsllq $42, %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpsrlq $22, %xmm1, %xmm1
|
||||
; CHECK-NEXT: vpor %xmm1, %xmm0, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
; XOP-LABEL: or_fshr_v2i64:
|
||||
; XOP: # %bb.0:
|
||||
; XOP-NEXT: vpsrlq $22, %xmm1, %xmm1
|
||||
; XOP-NEXT: vprotq $42, %xmm0, %xmm0
|
||||
; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0
|
||||
; XOP-NEXT: retq
|
||||
;
|
||||
; AVX512-LABEL: or_fshr_v2i64:
|
||||
; AVX512: # %bb.0:
|
||||
; AVX512-NEXT: vpsrlq $22, %xmm1, %xmm1
|
||||
; AVX512-NEXT: vprolq $42, %xmm0, %xmm0
|
||||
; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
|
||||
; AVX512-NEXT: retq
|
||||
%or1 = or <2 x i64> %x, %y
|
||||
%sh1 = shl <2 x i64> %x, <i64 42, i64 42>
|
||||
%sh2 = lshr <2 x i64> %or1, <i64 22, i64 22>
|
||||
|
|
|
|||
Loading…
Reference in New Issue