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Redefine count-leading 0s and 1s instructions. 

llvm-svn: 142216
This commit is contained in:
Akira Hatanaka 2011-10-17 18:26:37 +00:00
parent 42cf65fe51
commit 33fe8f908c
2 changed files with 17 additions and 20 deletions
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15
llvm/lib/Target/Mips/Mips64InstrInfo.td
View File

@ -57,15 +57,6 @@ class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
// Count Leading Ones/Zeros in Word
class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>:
FR<0x1c, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$src),
!strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
Requires<[HasBitCount]> {
let shamt = 0;
let rt = rd;
}
//===----------------------------------------------------------------------===//
// Instruction definition
//===----------------------------------------------------------------------===//
@ -150,10 +141,8 @@ def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>;
def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>;
/// Count Leading
def DCLZ : CountLeading64<0x24, "dclz",
[(set CPU64Regs:$dst, (ctlz CPU64Regs:$src))]>;
def DCLO : CountLeading64<0x25, "dclo",
[(set CPU64Regs:$dst, (ctlz (not CPU64Regs:$src)))]>;
def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;
def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions

22
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -513,9 +513,19 @@ class EffectiveAddress<string instr_asm> :
instr_asm, [(set CPURegs:$rt, addr:$addr)], IIAlu>;
// Count Leading Ones/Zeros in Word
class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
FR<0x1c, func, (outs CPURegs:$rd), (ins CPURegs:$rs),
!strconcat(instr_asm, "\t$rd, $rs"), pattern, IIAlu>,
class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
!strconcat(instr_asm, "\t$rd, $rs"),
[(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
Requires<[HasBitCount]> {
let shamt = 0;
let rt = rd;
}
class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
!strconcat(instr_asm, "\t$rd, $rs"),
[(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
Requires<[HasBitCount]> {
let shamt = 0;
let rt = rd;
@ -753,10 +763,8 @@ def SEB : SignExtInReg<0x10, "seb", i8>;
def SEH : SignExtInReg<0x18, "seh", i16>;
/// Count Leading
def CLZ : CountLeading<0x20, "clz",
[(set CPURegs:$rd, (ctlz CPURegs:$rs))]>;
def CLO : CountLeading<0x21, "clo",
[(set CPURegs:$rd, (ctlz (not CPURegs:$rs)))]>;
def CLZ : CountLeading0<0x20, "clz", CPURegs>;
def CLO : CountLeading1<0x21, "clo", CPURegs>;
/// Byte Swap
def WSBW : ByteSwap<0x20, 0x2, "wsbw">;