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[X86][SSE] Added extra (mul x, (1 << c)) -> x << c style vector tests 

vXi64 will benefit more from lowering to shifts than multiplies

llvm-svn: 284461
This commit is contained in:
Simon Pilgrim 2016-10-18 09:29:13 +00:00
parent e7c338081a
commit 33f138b566
1 changed files with 76 additions and 0 deletions
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76
llvm/test/CodeGen/X86/combine-mul.ll
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@ -103,6 +103,38 @@ define <4 x i32> @combine_vec_mul_pow2b(<4 x i32> %x) {
ret <4 x i32> %1
}
define <4 x i64> @combine_vec_mul_pow2c(<4 x i64> %x) {
; SSE-LABEL: combine_vec_mul_pow2c:
; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [1,2]
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: pmuludq %xmm2, %xmm3
; SSE-NEXT: psrlq $32, %xmm0
; SSE-NEXT: pmuludq %xmm2, %xmm0
; SSE-NEXT: psllq $32, %xmm0
; SSE-NEXT: paddq %xmm3, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [4,16]
; SSE-NEXT: movdqa %xmm1, %xmm3
; SSE-NEXT: pmuludq %xmm2, %xmm3
; SSE-NEXT: psrlq $32, %xmm1
; SSE-NEXT: pmuludq %xmm2, %xmm1
; SSE-NEXT: psllq $32, %xmm1
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_mul_pow2c:
; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [1,2,4,16]
; AVX-NEXT: vpmuludq %ymm1, %ymm0, %ymm2
; AVX-NEXT: vpsrlq $32, %ymm0, %ymm0
; AVX-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpsllq $32, %ymm0, %ymm0
; AVX-NEXT: vpaddq %ymm0, %ymm2, %ymm0
; AVX-NEXT: retq
%1 = mul <4 x i64> %x, <i64 1, i64 2, i64 4, i64 16>
ret <4 x i64> %1
}
; fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
define <4 x i32> @combine_vec_mul_negpow2a(<4 x i32> %x) {
; SSE-LABEL: combine_vec_mul_negpow2a:
@ -137,6 +169,50 @@ define <4 x i32> @combine_vec_mul_negpow2b(<4 x i32> %x) {
ret <4 x i32> %1
}
define <4 x i64> @combine_vec_mul_negpow2c(<4 x i64> %x) {
; SSE-LABEL: combine_vec_mul_negpow2c:
; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551615,18446744073709551614]
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: pmuludq %xmm2, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [4294967295,4294967295]
; SSE-NEXT: movdqa %xmm0, %xmm5
; SSE-NEXT: pmuludq %xmm4, %xmm5
; SSE-NEXT: psllq $32, %xmm5
; SSE-NEXT: psrlq $32, %xmm0
; SSE-NEXT: pmuludq %xmm2, %xmm0
; SSE-NEXT: psllq $32, %xmm0
; SSE-NEXT: paddq %xmm5, %xmm0
; SSE-NEXT: paddq %xmm3, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551612,18446744073709551600]
; SSE-NEXT: movdqa %xmm1, %xmm3
; SSE-NEXT: pmuludq %xmm2, %xmm3
; SSE-NEXT: pmuludq %xmm1, %xmm4
; SSE-NEXT: psllq $32, %xmm4
; SSE-NEXT: psrlq $32, %xmm1
; SSE-NEXT: pmuludq %xmm2, %xmm1
; SSE-NEXT: psllq $32, %xmm1
; SSE-NEXT: paddq %xmm4, %xmm1
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_mul_negpow2c:
; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [18446744073709551615,18446744073709551614,18446744073709551612,18446744073709551600]
; AVX-NEXT: vpmuludq %ymm1, %ymm0, %ymm2
; AVX-NEXT: vpbroadcastq {{.*}}(%rip), %ymm3
; AVX-NEXT: vpmuludq %ymm3, %ymm0, %ymm3
; AVX-NEXT: vpsllq $32, %ymm3, %ymm3
; AVX-NEXT: vpsrlq $32, %ymm0, %ymm0
; AVX-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpsllq $32, %ymm0, %ymm0
; AVX-NEXT: vpaddq %ymm0, %ymm3, %ymm0
; AVX-NEXT: vpaddq %ymm0, %ymm2, %ymm0
; AVX-NEXT: retq
%1 = mul <4 x i64> %x, <i64 -1, i64 -2, i64 -4, i64 -16>
ret <4 x i64> %1
}
; (mul (shl X, c1), c2) -> (mul X, c2 << c1)
define <4 x i32> @combine_vec_mul_shl_const(<4 x i32> %x) {
; SSE-LABEL: combine_vec_mul_shl_const: