[AArch64][GlobalISel] Select floating-point binary ops.

There is no FREM instruction, but the others are straightforward.

llvm-svn: 279081

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

@@ -146,6 +146,35 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID,
         return GenericOpc;
       }
     }
+  case AArch64::FPRRegBankID:
+    switch (OpSize) {
+    case 32:
+      switch (GenericOpc) {
+      case TargetOpcode::G_FADD:
+        return AArch64::FADDSrr;
+      case TargetOpcode::G_FSUB:
+        return AArch64::FSUBSrr;
+      case TargetOpcode::G_FMUL:
+        return AArch64::FMULSrr;
+      case TargetOpcode::G_FDIV:
+        return AArch64::FDIVSrr;
+      default:
+        return GenericOpc;
+      }
+    case 64:
+      switch (GenericOpc) {
+      case TargetOpcode::G_FADD:
+        return AArch64::FADDDrr;
+      case TargetOpcode::G_FSUB:
+        return AArch64::FSUBDrr;
+      case TargetOpcode::G_FMUL:
+        return AArch64::FMULDrr;
+      case TargetOpcode::G_FDIV:
+        return AArch64::FDIVDrr;
+      default:
+        return GenericOpc;
+      }
+    }
   };
   return GenericOpc;
 }
@@ -291,6 +320,11 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
 
+  case TargetOpcode::G_FADD:
+  case TargetOpcode::G_FSUB:
+  case TargetOpcode::G_FMUL:
+  case TargetOpcode::G_FDIV:
+
   case TargetOpcode::G_OR:
   case TargetOpcode::G_XOR:
   case TargetOpcode::G_AND:

llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp

@@ -46,6 +46,10 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
     for (auto Ty : {s32, s64})
       setAction(BinOp, Ty, Legal);
 
+  for (auto BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
+    for (auto Ty : {s32, s64})
+      setAction(BinOp, Ty, Legal);
+
   for (auto MemOp : {G_LOAD, G_STORE})
     for (auto Ty : {s32, s64})
       setAction(MemOp, Ty, Legal);

llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir

@@ -40,6 +40,18 @@
   define void @udiv_s32_gpr() { ret void }
   define void @udiv_s64_gpr() { ret void }
 
+  define void @fadd_s32_gpr() { ret void }
+  define void @fadd_s64_gpr() { ret void }
+
+  define void @fsub_s32_gpr() { ret void }
+  define void @fsub_s64_gpr() { ret void }
+
+  define void @fmul_s32_gpr() { ret void }
+  define void @fmul_s64_gpr() { ret void }
+
+  define void @fdiv_s32_gpr() { ret void }
+  define void @fdiv_s64_gpr() { ret void }
+
   define void @unconditional_br() { ret void }
 
   define void @load_s64_gpr(i64* %addr) { ret void }
@@ -718,6 +730,239 @@ body:             |
     %2(64) = G_UDIV s64 %0, %1
 ...
 
+---
+# Check that we select a s32 FPR G_FADD into FADDSrr.
+# CHECK-LABEL: name: fadd_s32_gpr
+name:            fadd_s32_gpr
+isSSA:           true
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: fpr32 }
+# CHECK-NEXT:  - { id: 1, class: fpr32 }
+# CHECK-NEXT:  - { id: 2, class: fpr32 }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %s0
+# CHECK:    %1 = COPY %s1
+# CHECK:    %2 = FADDSrr %0, %1
+body:             |
+  bb.0:
+    liveins: %s0, %s1
+
+    %0(32) = COPY %s0
+    %1(32) = COPY %s1
+    %2(32) = G_FADD s32 %0, %1
+...
+
+---
+# CHECK-LABEL: name: fadd_s64_gpr
+name:            fadd_s64_gpr
+isSSA:           true
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: fpr64 }
+# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 2, class: fpr64 }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %d0
+# CHECK:    %1 = COPY %d1
+# CHECK:    %2 = FADDDrr %0, %1
+body:             |
+  bb.0:
+    liveins: %d0, %d1
+
+    %0(64) = COPY %d0
+    %1(64) = COPY %d1
+    %2(64) = G_FADD s64 %0, %1
+...
+
+---
+# CHECK-LABEL: name: fsub_s32_gpr
+name:            fsub_s32_gpr
+isSSA:           true
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: fpr32 }
+# CHECK-NEXT:  - { id: 1, class: fpr32 }
+# CHECK-NEXT:  - { id: 2, class: fpr32 }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %s0
+# CHECK:    %1 = COPY %s1
+# CHECK:    %2 = FSUBSrr %0, %1
+body:             |
+  bb.0:
+    liveins: %s0, %s1
+
+    %0(32) = COPY %s0
+    %1(32) = COPY %s1
+    %2(32) = G_FSUB s32 %0, %1
+...
+
+---
+# CHECK-LABEL: name: fsub_s64_gpr
+name:            fsub_s64_gpr
+isSSA:           true
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: fpr64 }
+# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 2, class: fpr64 }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %d0
+# CHECK:    %1 = COPY %d1
+# CHECK:    %2 = FSUBDrr %0, %1
+body:             |
+  bb.0:
+    liveins: %d0, %d1
+
+    %0(64) = COPY %d0
+    %1(64) = COPY %d1
+    %2(64) = G_FSUB s64 %0, %1
+...
+
+---
+# CHECK-LABEL: name: fmul_s32_gpr
+name:            fmul_s32_gpr
+isSSA:           true
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: fpr32 }
+# CHECK-NEXT:  - { id: 1, class: fpr32 }
+# CHECK-NEXT:  - { id: 2, class: fpr32 }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %s0
+# CHECK:    %1 = COPY %s1
+# CHECK:    %2 = FMULSrr %0, %1
+body:             |
+  bb.0:
+    liveins: %s0, %s1
+
+    %0(32) = COPY %s0
+    %1(32) = COPY %s1
+    %2(32) = G_FMUL s32 %0, %1
+...
+
+---
+# CHECK-LABEL: name: fmul_s64_gpr
+name:            fmul_s64_gpr
+isSSA:           true
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: fpr64 }
+# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 2, class: fpr64 }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %d0
+# CHECK:    %1 = COPY %d1
+# CHECK:    %2 = FMULDrr %0, %1
+body:             |
+  bb.0:
+    liveins: %d0, %d1
+
+    %0(64) = COPY %d0
+    %1(64) = COPY %d1
+    %2(64) = G_FMUL s64 %0, %1
+...
+
+---
+# CHECK-LABEL: name: fdiv_s32_gpr
+name:            fdiv_s32_gpr
+isSSA:           true
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: fpr32 }
+# CHECK-NEXT:  - { id: 1, class: fpr32 }
+# CHECK-NEXT:  - { id: 2, class: fpr32 }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %s0
+# CHECK:    %1 = COPY %s1
+# CHECK:    %2 = FDIVSrr %0, %1
+body:             |
+  bb.0:
+    liveins: %s0, %s1
+
+    %0(32) = COPY %s0
+    %1(32) = COPY %s1
+    %2(32) = G_FDIV s32 %0, %1
+...
+
+---
+# CHECK-LABEL: name: fdiv_s64_gpr
+name:            fdiv_s64_gpr
+isSSA:           true
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: fpr64 }
+# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 2, class: fpr64 }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %d0
+# CHECK:    %1 = COPY %d1
+# CHECK:    %2 = FDIVDrr %0, %1
+body:             |
+  bb.0:
+    liveins: %d0, %d1
+
+    %0(64) = COPY %d0
+    %1(64) = COPY %d1
+    %2(64) = G_FDIV s64 %0, %1
+...
+
 ---
 # CHECK-LABEL: name: unconditional_br
 name:            unconditional_br