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[X86][BtVer2] Remove 128-bit F16C InstRW overrides. 

These are already handled identically by WriteCvtF2F.

llvm-svn: 330318
This commit is contained in:
Simon Pilgrim 2018-04-19 11:16:33 +00:00
parent b04cd1b9f3
commit 33dede9075
1 changed files with 0 additions and 10 deletions
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10
llvm/lib/Target/X86/X86ScheduleBtVer2.td
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@ -502,21 +502,11 @@ def : InstRW<[JWriteINSERTQ], (instrs INSERTQ, INSERTQI)>;
// F16C instructions. // F16C instructions.
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
def JWriteCVT3: SchedWriteRes<[JFPU1, JSTC]> {
let Latency = 3;
}
def : InstRW<[JWriteCVT3], (instrs VCVTPS2PHrr, VCVTPH2PSrr)>;
def JWriteCVT3St: SchedWriteRes<[JFPU1, JSTC, JSAGU]> { def JWriteCVT3St: SchedWriteRes<[JFPU1, JSTC, JSAGU]> {
let Latency = 3; let Latency = 3;
} }
def : InstRW<[JWriteCVT3St], (instrs VCVTPS2PHmr)>; def : InstRW<[JWriteCVT3St], (instrs VCVTPS2PHmr)>;
def JWriteCVT3Ld: SchedWriteRes<[JLAGU, JFPU1, JSTC]> {
let Latency = 8;
}
def : InstRW<[JWriteCVT3Ld], (instrs VCVTPH2PSrm)>;
def JWriteCVTPS2PHY: SchedWriteRes<[JFPU1, JSTC, JFPX]> { def JWriteCVTPS2PHY: SchedWriteRes<[JFPU1, JSTC, JFPX]> {
let Latency = 6; let Latency = 6;
let ResourceCycles = [2, 2, 2]; let ResourceCycles = [2, 2, 2];