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[AArch64] Decouple zero store promotion from narrow ld merge. NFC. 

Summary: This change refactors to decouple the zero store promotion from the narrow ld merge and add a flag (enable-narrow-ld-merge=true) to control the narrow ld merge optimization.

Reviewers: jmolloy, t.p.northover, mcrosier

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D19885

llvm-svn: 268744
This commit is contained in:
Jun Bum Lim 2016-05-06 15:08:57 +00:00
parent 5b9ac41c13
commit 33be4997ed
1 changed files with 16 additions and 28 deletions
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44
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
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@ -51,6 +51,10 @@ static cl::opt<unsigned> LdStLimit("aarch64-load-store-scan-limit",
static cl::opt<unsigned> UpdateLimit("aarch64-update-scan-limit", cl::init(100),
cl::Hidden);
static cl::opt<bool> EnableNarrowLdMerge("enable-narrow-ld-merge", cl::Hidden,
cl::init(true),
cl::desc("Enable narrow load merge"));
namespace llvm {
void initializeAArch64LoadStoreOptPass(PassRegistry &);
}
@ -614,11 +618,14 @@ static bool isLdOffsetInRangeOfSt(MachineInstr *LoadInst,
(UnscaledLdOffset + LoadSize <= (UnscaledStOffset + StoreSize));
}
static bool isPromotableZeroStoreOpcode(MachineInstr *MI) {
unsigned Opc = MI->getOpcode();
static bool isPromotableZeroStoreOpcode(unsigned Opc) {
return isNarrowStore(Opc) || Opc == AArch64::STRWui || Opc == AArch64::STURWi;
}
static bool isPromotableZeroStoreOpcode(MachineInstr *MI) {
return isPromotableZeroStoreOpcode(MI->getOpcode());
}
static bool isPromotableZeroStoreInst(MachineInstr *MI) {
return (isPromotableZeroStoreOpcode(MI)) &&
getLdStRegOp(MI).getReg() == AArch64::WZR;
@ -1722,36 +1729,17 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
enableNarrowLdOpt && MBBI != E;) {
MachineInstr *MI = MBBI;
switch (MI->getOpcode()) {
default:
// Just move on to the next instruction.
++MBBI;
break;
// Scaled instructions.
case AArch64::LDRBBui:
case AArch64::LDRHHui:
case AArch64::LDRSBWui:
case AArch64::LDRSHWui:
case AArch64::STRBBui:
case AArch64::STRHHui:
case AArch64::STRWui:
// Unscaled instructions.
case AArch64::LDURBBi:
case AArch64::LDURHHi:
case AArch64::LDURSBWi:
case AArch64::LDURSHWi:
case AArch64::STURBBi:
case AArch64::STURHHi:
case AArch64::STURWi: {
unsigned Opc = MI->getOpcode();
if (isPromotableZeroStoreOpcode(Opc) ||
(EnableNarrowLdMerge && isNarrowLoad(Opc))) {
if (tryToMergeLdStInst(MBBI)) {
Modified = true;
break;
}
} else
++MBBI;
} else
++MBBI;
break;
}
}
}
// 3) Find loads and stores that can be merged into a single load or store
// pair instruction.
// e.g.,