maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[AVX512] Stop treating VR512 specially in getLoadStoreRegOpcode and use the regular switch which already tried to handle it, but was unreachable. This has the added benefit of enabling aligned loads/stores if the stack is aligned. 

llvm-svn: 277302
This commit is contained in:
Craig Topper 2016-07-31 20:19:53 +00:00
parent 2a6bbb8203
commit 338ec9a0cb
2 changed files with 5 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -4845,8 +4845,6 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg,
return load ? X86::VMOVSSZrm : X86::VMOVSSZmr; return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC)) if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
return load ? X86::VMOVSDZrm : X86::VMOVSDZmr; return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
if (X86::VR512RegClass.hasSubClassEq(RC))
return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
} }
bool HasAVX = STI.hasAVX(); bool HasAVX = STI.hasAVX();
@ -4924,7 +4922,7 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg,
return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr; return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr;
case 64: case 64:
assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass"); assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
assert(STI.hasVLX() && "Using 512-bit register requires AVX512"); assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
if (isStackAligned) if (isStackAligned)
return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr; return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
else else

8
llvm/test/CodeGen/X86/avx512-intel-ocl.ll
View File

@ -62,11 +62,11 @@ define <16 x float> @testf16_regs(<16 x float> %a, <16 x float> %b) nounwind {
; test calling conventions - prolog and epilog ; test calling conventions - prolog and epilog
; WIN64-LABEL: test_prolog_epilog ; WIN64-LABEL: test_prolog_epilog
; WIN64: vmovups %zmm21, {{.*(%rbp).*}} # 64-byte Spill ; WIN64: vmovaps %zmm21, {{.*(%rbp).*}} # 64-byte Spill
; WIN64: vmovups %zmm6, {{.*(%rbp).*}} # 64-byte Spill ; WIN64: vmovaps %zmm6, {{.*(%rbp).*}} # 64-byte Spill
; WIN64: call ; WIN64: call
; WIN64: vmovups {{.*(%rbp).*}}, %zmm6 # 64-byte Reload ; WIN64: vmovaps {{.*(%rbp).*}}, %zmm6 # 64-byte Reload
; WIN64: vmovups {{.*(%rbp).*}}, %zmm21 # 64-byte Reload ; WIN64: vmovaps {{.*(%rbp).*}}, %zmm21 # 64-byte Reload
; X64-LABEL: test_prolog_epilog ; X64-LABEL: test_prolog_epilog
; X64: kmovq %k7, {{.*}}(%rsp) ## 8-byte Spill ; X64: kmovq %k7, {{.*}}(%rsp) ## 8-byte Spill