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Do not treat atomic.load.sub differently than other atomic binary intrinsics. 

llvm-svn: 135418
This commit is contained in:
Akira Hatanaka 2011-07-18 19:58:59 +00:00
parent 9a5b16b87c
commit 338879a7f4
2 changed files with 4 additions and 15 deletions
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14
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -819,7 +819,6 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
unsigned Tmp3 = RegInfo.createVirtualRegister(RC);
unsigned Tmp4 = RegInfo.createVirtualRegister(RC);
unsigned Tmp5 = RegInfo.createVirtualRegister(RC);
unsigned Tmp6 = RegInfo.createVirtualRegister(RC);
unsigned Tmp7 = RegInfo.createVirtualRegister(RC);
unsigned Tmp8 = RegInfo.createVirtualRegister(RC);
@ -863,14 +862,8 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm);
BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift);
BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
if (BinOpcode != Mips::SUBu) {
BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Incr).addImm(MaskImm);
BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp4).addReg(Shift);
} else {
BuildMI(BB, dl, TII->get(Mips::SUBu), Tmp4).addReg(Mips::ZERO).addReg(Incr);
BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Tmp4).addImm(MaskImm);
BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp5).addReg(Shift);
}
BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Incr).addImm(MaskImm);
BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp4).addReg(Shift);
BB->addSuccessor(loopMBB);
@ -899,9 +892,6 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
// nor tmp7, $0, tmp6
BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval).addReg(Incr2);
BuildMI(BB, dl, TII->get(Mips::NOR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6);
} else if (BinOpcode == Mips::SUBu) {
// addu tmp7, oldval, incr2
BuildMI(BB, dl, TII->get(Mips::ADDu), Tmp7).addReg(Oldval).addReg(Incr2);
} else if (BinOpcode) {
// <binop> tmp7, oldval, incr2
BuildMI(BB, dl, TII->get(BinOpcode), Tmp7).addReg(Oldval).addReg(Incr2);

5
llvm/test/CodeGen/Mips/atomic.ll
View File

@ -129,13 +129,12 @@ entry:
; CHECK: ori $[[R5:[0-9]+]], $zero, 255
; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
; CHECK: subu $[[R18:[0-9]+]], $zero, $4
; CHECK: andi $[[R8:[0-9]+]], $[[R18]], 255
; CHECK: andi $[[R8:[0-9]+]], $4, 255
; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
; CHECK: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]