forked from OSchip/llvm-project
[X86] Remove PALIGNR/VALIGN handling from combineBitcastForMaskedOp and move to isel patterns instead. Prefer 128-bit VALIGND/VALIGNQ over PALIGNR during lowering when possible.
llvm-svn: 317299
This commit is contained in:
Craig Topper
parent
2fda36a18e
commit
333897ec31
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@ -10716,10 +10716,16 @@ static SDValue lowerV2I64VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask,
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// Try to use byte rotation instructions.
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// Its more profitable for pre-SSSE3 to use shuffles/unpacks.
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if (Subtarget.hasSSSE3())
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if (Subtarget.hasSSSE3()) {
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if (Subtarget.hasVLX())
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if (SDValue Rotate = lowerVectorShuffleAsRotate(DL, MVT::v2i64, V1, V2,
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Mask, Subtarget, DAG))
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return Rotate;
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if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
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DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
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return Rotate;
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}
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// If we have direct support for blends, we should lower by decomposing into
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// a permute. That will be faster than the domain cross.
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@ -11016,10 +11022,16 @@ static SDValue lowerV4I32VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask,
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// Try to use byte rotation instructions.
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// Its more profitable for pre-SSSE3 to use shuffles/unpacks.
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if (Subtarget.hasSSSE3())
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if (Subtarget.hasSSSE3()) {
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if (Subtarget.hasVLX())
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if (SDValue Rotate = lowerVectorShuffleAsRotate(DL, MVT::v4i32, V1, V2,
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Mask, Subtarget, DAG))
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return Rotate;
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if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
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DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
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return Rotate;
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}
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// Assume that a single SHUFPS is faster than an alternative sequence of
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// multiple instructions (even if the CPU has a domain penalty).
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@ -30674,26 +30686,6 @@ static bool combineBitcastForMaskedOp(SDValue OrigOp, SelectionDAG &DAG,
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unsigned Opcode = Op.getOpcode();
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switch (Opcode) {
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case X86ISD::PALIGNR:
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// PALIGNR can be converted to VALIGND/Q for 128-bit vectors.
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if (!VT.is128BitVector())
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return false;
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Opcode = X86ISD::VALIGN;
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LLVM_FALLTHROUGH;
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case X86ISD::VALIGN: {
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if (EltVT != MVT::i32 && EltVT != MVT::i64)
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return false;
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uint64_t Imm = Op.getConstantOperandVal(2);
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MVT OpEltVT = Op.getSimpleValueType().getVectorElementType();
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unsigned ShiftAmt = Imm * OpEltVT.getSizeInBits();
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unsigned EltSize = EltVT.getSizeInBits();
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// Make sure we can represent the same shift with the new VT.
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if ((ShiftAmt % EltSize) != 0)
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return false;
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Imm = ShiftAmt / EltSize;
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return BitcastAndCombineShuffle(Opcode, Op.getOperand(0), Op.getOperand(1),
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DAG.getConstant(Imm, DL, MVT::i8));
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}
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case X86ISD::SHUF128: {
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if (EltVT.getSizeInBits() != 32 && EltVT.getSizeInBits() != 64)
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return false;
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@ -8911,6 +8911,123 @@ defm VPALIGNR: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
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avx512vl_i8_info, avx512vl_i8_info>,
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EVEX_CD8<8, CD8VF>;
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// Fragments to help convert valignq into masked valignd. Or valignq/valignd
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// into vpalignr.
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def ValignqImm32XForm : SDNodeXForm<imm, [{
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return getI8Imm(N->getZExtValue() * 2, SDLoc(N));
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}]>;
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def ValignqImm8XForm : SDNodeXForm<imm, [{
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return getI8Imm(N->getZExtValue() * 8, SDLoc(N));
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}]>;
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def ValigndImm8XForm : SDNodeXForm<imm, [{
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return getI8Imm(N->getZExtValue() * 4, SDLoc(N));
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}]>;
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multiclass avx512_vpalign_mask_lowering<string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo From, X86VectorVTInfo To,
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SDNodeXForm ImmXForm> {
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def : Pat<(To.VT (vselect To.KRCWM:$mask,
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(bitconvert
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(From.VT (OpNode From.RC:$src1, From.RC:$src2,
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imm:$src3))),
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To.RC:$src0)),
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(!cast<Instruction>(OpcodeStr#"rrik") To.RC:$src0, To.KRCWM:$mask,
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To.RC:$src1, To.RC:$src2,
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(ImmXForm imm:$src3))>;
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def : Pat<(To.VT (vselect To.KRCWM:$mask,
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(bitconvert
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(From.VT (OpNode From.RC:$src1, From.RC:$src2,
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imm:$src3))),
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To.ImmAllZerosV)),
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(!cast<Instruction>(OpcodeStr#"rrikz") To.KRCWM:$mask,
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To.RC:$src1, To.RC:$src2,
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(ImmXForm imm:$src3))>;
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def : Pat<(To.VT (vselect To.KRCWM:$mask,
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(bitconvert
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(From.VT (OpNode From.RC:$src1,
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(bitconvert (To.LdFrag addr:$src2)),
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imm:$src3))),
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To.RC:$src0)),
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(!cast<Instruction>(OpcodeStr#"rmik") To.RC:$src0, To.KRCWM:$mask,
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To.RC:$src1, addr:$src2,
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(ImmXForm imm:$src3))>;
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def : Pat<(To.VT (vselect To.KRCWM:$mask,
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(bitconvert
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(From.VT (OpNode From.RC:$src1,
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(bitconvert (To.LdFrag addr:$src2)),
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imm:$src3))),
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To.ImmAllZerosV)),
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(!cast<Instruction>(OpcodeStr#"rmikz") To.KRCWM:$mask,
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To.RC:$src1, addr:$src2,
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(ImmXForm imm:$src3))>;
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}
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multiclass avx512_vpalign_mask_lowering_mb<string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo From,
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X86VectorVTInfo To,
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SDNodeXForm ImmXForm> :
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avx512_vpalign_mask_lowering<OpcodeStr, OpNode, From, To, ImmXForm> {
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def : Pat<(From.VT (OpNode From.RC:$src1,
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(bitconvert (To.VT (X86VBroadcast
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(To.ScalarLdFrag addr:$src2)))),
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imm:$src3)),
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(!cast<Instruction>(OpcodeStr#"rmbi") To.RC:$src1, addr:$src2,
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(ImmXForm imm:$src3))>;
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def : Pat<(To.VT (vselect To.KRCWM:$mask,
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(bitconvert
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(From.VT (OpNode From.RC:$src1,
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(bitconvert
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(To.VT (X86VBroadcast
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(To.ScalarLdFrag addr:$src2)))),
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imm:$src3))),
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To.RC:$src0)),
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(!cast<Instruction>(OpcodeStr#"rmbik") To.RC:$src0, To.KRCWM:$mask,
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To.RC:$src1, addr:$src2,
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(ImmXForm imm:$src3))>;
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def : Pat<(To.VT (vselect To.KRCWM:$mask,
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(bitconvert
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(From.VT (OpNode From.RC:$src1,
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(bitconvert
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(To.VT (X86VBroadcast
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(To.ScalarLdFrag addr:$src2)))),
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imm:$src3))),
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To.ImmAllZerosV)),
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(!cast<Instruction>(OpcodeStr#"rmbikz") To.KRCWM:$mask,
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To.RC:$src1, addr:$src2,
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(ImmXForm imm:$src3))>;
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}
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let Predicates = [HasAVX512] in {
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// For 512-bit we lower to the widest element type we can. So we only need
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// to handle converting valignq to valignd.
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defm : avx512_vpalign_mask_lowering_mb<"VALIGNDZ", X86VAlign, v8i64_info,
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v16i32_info, ValignqImm32XForm>;
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}
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let Predicates = [HasVLX] in {
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// For 128-bit we lower to the widest element type we can. So we only need
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// to handle converting valignq to valignd.
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defm : avx512_vpalign_mask_lowering_mb<"VALIGNDZ128", X86VAlign, v2i64x_info,
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v4i32x_info, ValignqImm32XForm>;
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// For 256-bit we lower to the widest element type we can. So we only need
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// to handle converting valignq to valignd.
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defm : avx512_vpalign_mask_lowering_mb<"VALIGNDZ256", X86VAlign, v4i64x_info,
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v8i32x_info, ValignqImm32XForm>;
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}
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let Predicates = [HasVLX, HasBWI] in {
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// We can turn 128 and 256 bit VALIGND/VALIGNQ into VPALIGNR.
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defm : avx512_vpalign_mask_lowering<"VPALIGNRZ128", X86VAlign, v2i64x_info,
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v16i8x_info, ValignqImm8XForm>;
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defm : avx512_vpalign_mask_lowering<"VPALIGNRZ128", X86VAlign, v4i32x_info,
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v16i8x_info, ValigndImm8XForm>;
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}
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defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
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avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
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@ -4712,8 +4712,8 @@ declare <8 x i32> @llvm.x86.avx512.mask.valign.d.256(<8 x i32>, <8 x i32>, i32,
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define <8 x i32>@test_int_x86_avx512_mask_valign_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x3, i8 %x4) {
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; CHECK-LABEL: test_int_x86_avx512_mask_valign_d_256:
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; CHECK: ## BB#0:
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; CHECK-NEXT: valignd $6, %ymm1, %ymm0, %ymm3 ## encoding: [0x62,0xf3,0x7d,0x28,0x03,0xd9,0x06]
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; CHECK-NEXT: ## ymm3 = ymm1[6,7],ymm0[0,1,2,3,4,5]
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; CHECK-NEXT: valignq $3, %ymm1, %ymm0, %ymm3 ## encoding: [0x62,0xf3,0xfd,0x28,0x03,0xd9,0x03]
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; CHECK-NEXT: ## ymm3 = ymm1[3],ymm0[0,1,2]
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; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
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; CHECK-NEXT: valignd $6, %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf3,0x7d,0x29,0x03,0xd1,0x06]
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; CHECK-NEXT: ## ymm2 {%k1} = ymm1[6,7],ymm0[0,1,2,3,4,5]
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