forked from OSchip/llvm-project
After reducing the size of an operation in the DAG we zero-extend the reduced
bitwidth op back to the original size. If we reduce ANDs then this can cause an endless loop. This patch changes the ZEXT to ANY_EXTEND if the demanded bits are equal or smaller than the size of the reduced operation. llvm-svn: 170505
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@ -1161,7 +1161,8 @@ TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
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// Search for the smallest integer type with free casts to and from
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// Op's type. For expedience, just check power-of-2 integer types.
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
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unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
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unsigned SmallVTBits = DemandedSize;
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if (!isPowerOf2_32(SmallVTBits))
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SmallVTBits = NextPowerOf2(SmallVTBits);
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for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
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@ -1174,7 +1175,9 @@ TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
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Op.getNode()->getOperand(0)),
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DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
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Op.getNode()->getOperand(1)));
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SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
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bool NeedZext = DemandedSize > SmallVTBits;
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SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
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dl, Op.getValueType(), X);
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return CombineTo(Op, Z);
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}
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}
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@ -0,0 +1,21 @@
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; RUN: llc < %s
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define void @main() {
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if.end:
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br label %block.i.i
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block.i.i:
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%tmpbb = load i8* undef
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%tmp54 = zext i8 %tmpbb to i64
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%tmp59 = and i64 %tmp54, 8
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%tmp60 = add i64 %tmp59, 3691045929300498764
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%tmp62 = sub i64 %tmp60, 3456506383779105993
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%tmp63 = xor i64 1050774804270620004, %tmp62
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%tmp65 = xor i64 %tmp62, 234539545521392771
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%tmp67 = or i64 %tmp65, %tmp63
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%tmp71 = xor i64 %tmp67, 6781485823212740913
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%tmp72 = trunc i64 %tmp71 to i32
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%tmp74 = lshr i32 2, %tmp72
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store i32 %tmp74, i32* undef
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br label %block.i.i
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}
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