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Change the SREM case to match the logic in the IR version ComputeMaskedBits. 

llvm-svn: 94805
This commit is contained in:
Duncan Sands 2010-01-29 09:45:26 +00:00
parent 297a494f55
commit 3327498095
1 changed files with 18 additions and 9 deletions
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27
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -1925,19 +1925,28 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
}
case ISD::SREM:
if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
const APInt &RA = Rem->getAPIntValue();
if (RA.isPowerOf2() || (-RA).isPowerOf2()) {
APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA;
const APInt &RA = Rem->getAPIntValue().abs();
if (RA.isPowerOf2()) {
APInt LowBits = RA - 1;
APInt Mask2 = LowBits | APInt::getSignBit(BitWidth);
ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1);
// If the sign bit of the first operand is zero, the sign bit of
// the result is zero. If the first operand has no one bits below
// the second operand's single 1 bit, its sign will be zero.
if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits))
KnownZero2 |= ~LowBits;
// The low bits of the first operand are unchanged by the srem.
KnownZero = KnownZero2 & LowBits;
KnownOne = KnownOne2 & LowBits;
KnownZero |= KnownZero2 & Mask;
// If the first operand is non-negative or has all low bits zero, then
// the upper bits are all zero.
if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits))
KnownZero |= ~LowBits;
// If the first operand is negative and not all low bits are zero, then
// the upper bits are all one.
if (KnownOne2[BitWidth-1] && ((KnownOne2 & LowBits) != 0))
KnownOne |= ~LowBits;
KnownZero &= Mask;
KnownOne &= Mask;
assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
}