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TableGen: Store all allocation orders together. 

There is no need to keep the primary order separate.

llvm-svn: 141082
This commit is contained in:
Jakob Stoklund Olesen 2011-10-04 15:28:44 +00:00
parent bd92dc608d
commit 331534e5bb
2 changed files with 15 additions and 14 deletions
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18
llvm/utils/TableGen/CodeGenRegisters.cpp
View File

@ -273,18 +273,22 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
} }
assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!"); assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
// Allocation order 0 is the full set. AltOrders provides others.
const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
ListInit *AltOrders = R->getValueAsListInit("AltOrders");
Orders.resize(1 + AltOrders->size());
// Default allocation order always contains all registers. // Default allocation order always contains all registers.
Elements = RegBank.getSets().expand(R); for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
for (unsigned i = 0, e = Elements->size(); i != e; ++i) Orders[0].push_back((*Elements)[i]);
Members.insert(RegBank.getReg((*Elements)[i])); Members.insert(RegBank.getReg((*Elements)[i]));
}
// Alternative allocation orders may be subsets. // Alternative allocation orders may be subsets.
ListInit *Alts = R->getValueAsListInit("AltOrders");
AltOrders.resize(Alts->size());
SetTheory::RecSet Order; SetTheory::RecSet Order;
for (unsigned i = 0, e = Alts->size(); i != e; ++i) { for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
RegBank.getSets().evaluate(Alts->getElement(i), Order); RegBank.getSets().evaluate(AltOrders->getElement(i), Order);
AltOrders[i].append(Order.begin(), Order.end()); Orders[1 + i].append(Order.begin(), Order.end());
// Verify that all altorder members are regclass members. // Verify that all altorder members are regclass members.
while (!Order.empty()) { while (!Order.empty()) {
CodeGenRegister *Reg = RegBank.getReg(Order.back()); CodeGenRegister *Reg = RegBank.getReg(Order.back());

11
llvm/utils/TableGen/CodeGenRegisters.h
View File

@ -86,8 +86,8 @@ namespace llvm {
class CodeGenRegisterClass { class CodeGenRegisterClass {
CodeGenRegister::Set Members; CodeGenRegister::Set Members;
const std::vector<Record*> *Elements; // Allocation orders. Order[0] always contains all registers in Members.
std::vector<SmallVector<Record*, 16> > AltOrders; std::vector<SmallVector<Record*, 16> > Orders;
// Bit mask of sub-classes including this, indexed by their EnumValue. // Bit mask of sub-classes including this, indexed by their EnumValue.
BitVector SubClasses; BitVector SubClasses;
// List of super-classes, topologocally ordered to have the larger classes // List of super-classes, topologocally ordered to have the larger classes
@ -154,14 +154,11 @@ namespace llvm {
// The order of registers is the same as in the .td file. // The order of registers is the same as in the .td file.
// No = 0 is the default allocation order, No = 1 is the first alternative. // No = 0 is the default allocation order, No = 1 is the first alternative.
ArrayRef<Record*> getOrder(unsigned No = 0) const { ArrayRef<Record*> getOrder(unsigned No = 0) const {
if (No == 0) return Orders[No];
return *Elements;
else
return AltOrders[No - 1];
} }
// Return the total number of allocation orders available. // Return the total number of allocation orders available.
unsigned getNumOrders() const { return 1 + AltOrders.size(); } unsigned getNumOrders() const { return Orders.size(); }
// Get the set of registers. This set contains the same registers as // Get the set of registers. This set contains the same registers as
// getOrder(0). // getOrder(0).