From 32f6a15dfd5221d5fb628f74ecfe72302af460f4 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Wed, 24 Mar 2021 23:55:58 -0700
Subject: [PATCH] [RISCV] Add more tests that can be improved by D99042.

---
 llvm/test/CodeGen/RISCV/alu32.ll   | 23 ++++++++++++++++++++
 llvm/test/CodeGen/RISCV/rv64zba.ll | 34 ++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+)

diff --git a/llvm/test/CodeGen/RISCV/alu32.ll b/llvm/test/CodeGen/RISCV/alu32.ll
index 975716e53c04..fa0c4bbf3b34 100644
--- a/llvm/test/CodeGen/RISCV/alu32.ll
+++ b/llvm/test/CodeGen/RISCV/alu32.ll
@@ -129,6 +129,29 @@ define i32 @srli(i32 %a) nounwind {
   ret i32 %1
 }
 
+; FIXME: This should use srliw on RV64, but SimplifyDemandedBits breaks the
+; (and X, 0xffffffff) that type legalization inserts.
+define i32 @srli_demandedbits(i32 %0) {
+; RV32I-LABEL: srli_demandedbits:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a0, a0, 3
+; RV32I-NEXT:    ori a0, a0, 1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: srli_demandedbits:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 1
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    addi a1, a1, -16
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    srli a0, a0, 3
+; RV64I-NEXT:    ori a0, a0, 1
+; RV64I-NEXT:    ret
+  %2 = lshr i32 %0, 3
+  %3 = or i32 %2, 1
+  ret i32 %3
+}
+
 define i32 @srai(i32 %a) nounwind {
 ; RV32I-LABEL: srai:
 ; RV32I:       # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index 9dcbaae60822..3174ecc153ce 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -126,6 +126,40 @@ define i64 @zextw_i64(i64 %a) nounwind {
   ret i64 %and
 }
 
+; FIXME: This can use zext.w, but we need targetShrinkDemandedConstant to
+; to adjust the immediate.
+define i64 @zextw_demandedbits_i64(i64 %0) {
+; RV64I-LABEL: zextw_demandedbits_i64:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 1
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    addi a1, a1, -2
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ori a0, a0, 1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: zextw_demandedbits_i64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 1
+; RV64IB-NEXT:    slli a1, a1, 32
+; RV64IB-NEXT:    addi a1, a1, -2
+; RV64IB-NEXT:    and a0, a0, a1
+; RV64IB-NEXT:    ori a0, a0, 1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: zextw_demandedbits_i64:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 1
+; RV64IBA-NEXT:    slli a1, a1, 32
+; RV64IBA-NEXT:    addi a1, a1, -2
+; RV64IBA-NEXT:    and a0, a0, a1
+; RV64IBA-NEXT:    ori a0, a0, 1
+; RV64IBA-NEXT:    ret
+  %2 = and i64 %0, 4294967294
+  %3 = or i64 %2, 1
+  ret i64 %3
+}
+
 define signext i16 @sh1add(i64 %0, i16* %1) {
 ; RV64I-LABEL: sh1add:
 ; RV64I:       # %bb.0: