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Be a little bit more specific about target for the memory barrier 

instructions.

llvm-svn: 110360
This commit is contained in:
Eric Christopher 2010-08-05 18:36:20 +00:00
parent 4abffad17c
commit 32f5d6b9be
2 changed files with 4 additions and 2 deletions
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3
llvm/lib/Target/X86/X86Instr64bit.td
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@ -1624,7 +1624,8 @@ let Defs = [ESP] in
def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero), def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero),
"lock\n\t" "lock\n\t"
"or{q}\t{$zero, (%rsp)|(%rsp), $zero}", "or{q}\t{$zero, (%rsp)|(%rsp), $zero}",
[(X86MemBarrierNoSSE GR64:$zero)]>, LOCK; [(X86MemBarrierNoSSE GR64:$zero)]>,
Requires<[In64BitMode]>, LOCK;
let Defs = [RAX, EFLAGS], Uses = [RAX] in { let Defs = [RAX, EFLAGS], Uses = [RAX] in {
def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap), def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),

3
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -3938,7 +3938,8 @@ let Defs = [ESP] in
def Int_MemBarrierNoSSE : I<0x09, MRM1r, (outs), (ins GR32:$zero), def Int_MemBarrierNoSSE : I<0x09, MRM1r, (outs), (ins GR32:$zero),
"lock\n\t" "lock\n\t"
"or{l}\t{$zero, (%esp)|(%esp), $zero}", "or{l}\t{$zero, (%esp)|(%esp), $zero}",
[(X86MemBarrierNoSSE GR32:$zero)]>, LOCK; [(X86MemBarrierNoSSE GR32:$zero)]>,
Requires<[In32BitMode]>, LOCK;
} }
// Atomic swap. These are just normal xchg instructions. But since a memory // Atomic swap. These are just normal xchg instructions. But since a memory