From 32e90cbcd19a83e20a86bfc1cbf7cec9729e9077 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Fri, 13 Mar 2020 10:58:19 -0700 Subject: [PATCH] [AMDGPU] Disable endcf collapse There are some functional regressions and I suspect our scopes are not as perfectly enclosed as I expected. Disable it for now. Differential Revision: https://reviews.llvm.org/D76148 --- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 23 ++++++++++++------- llvm/test/CodeGen/AMDGPU/collapse-endcf.ll | 2 +- llvm/test/CodeGen/AMDGPU/collapse-endcf.mir | 2 +- .../CodeGen/AMDGPU/mul24-pass-ordering.ll | 6 +++-- 4 files changed, 21 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp index 6e617df5f28f..de9d8fa29005 100644 --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -74,6 +74,10 @@ using namespace llvm; #define DEBUG_TYPE "si-lower-control-flow" +static cl::opt +RemoveRedundantEndcf("amdgpu-remove-redundant-endcf", + cl::init(false), cl::ReallyHidden); + namespace { class SILowerControlFlow : public MachineFunctionPass { @@ -444,14 +448,17 @@ void SILowerControlFlow::emitEndCf(MachineInstr &MI) { // If the only instruction immediately following this END_CF is an another // END_CF in the only successor we can avoid emitting exec mask restore here. - auto Next = skipIgnoreExecInstsTrivialSucc(MBB, std::next(MI.getIterator())); - if (Next != MBB.end() && (Next->getOpcode() == AMDGPU::SI_END_CF || - LoweredEndCf.count(&*Next))) { - LLVM_DEBUG(dbgs() << "Skip redundant "; MI.dump()); - if (LIS) - LIS->RemoveMachineInstrFromMaps(MI); - MI.eraseFromParent(); - return; + if (RemoveRedundantEndcf) { + auto Next = + skipIgnoreExecInstsTrivialSucc(MBB, std::next(MI.getIterator())); + if (Next != MBB.end() && (Next->getOpcode() == AMDGPU::SI_END_CF || + LoweredEndCf.count(&*Next))) { + LLVM_DEBUG(dbgs() << "Skip redundant "; MI.dump()); + if (LIS) + LIS->RemoveMachineInstrFromMaps(MI); + MI.eraseFromParent(); + return; + } } MachineBasicBlock::iterator InsPt = diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll index a37bf104e370..c2676eaeb989 100644 --- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll +++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-remove-redundant-endcf < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; GCN-LABEL: {{^}}simple_nested_if: ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]] diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir b/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir index a21ecdc6f975..277797fc2fba 100644 --- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir +++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=si-lower-control-flow %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=si-lower-control-flow -amdgpu-remove-redundant-endcf %s -o - | FileCheck -check-prefix=GCN %s # Make sure dbg_value doesn't change codeegn when collapsing end_cf --- diff --git a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll index 5f0b5aaecac9..9f717df480fb 100644 --- a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll +++ b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll @@ -58,7 +58,7 @@ define void @lsr_order_mul24_1(i32 %arg, i32 %arg1, i32 %arg2, float addrspace(3 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5 ; GFX9-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1 ; GFX9-NEXT: s_and_saveexec_b64 s[10:11], s[4:5] -; GFX9-NEXT: s_cbranch_execz BB1_3 +; GFX9-NEXT: s_cbranch_execz BB1_4 ; GFX9-NEXT: ; %bb.1: ; %bb19 ; GFX9-NEXT: v_cvt_f32_u32_e32 v7, v6 ; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v6 @@ -100,7 +100,9 @@ define void @lsr_order_mul24_1(i32 %arg, i32 %arg1, i32 %arg2, float addrspace(3 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v6 ; GFX9-NEXT: s_andn2_b64 exec, exec, s[12:13] ; GFX9-NEXT: s_cbranch_execnz BB1_2 -; GFX9-NEXT: BB1_3: ; %Flow3 +; GFX9-NEXT: ; %bb.3: ; %Flow +; GFX9-NEXT: s_or_b64 exec, exec, s[12:13] +; GFX9-NEXT: BB1_4: ; %Flow3 ; GFX9-NEXT: s_or_b64 exec, exec, s[10:11] ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31]