forked from OSchip/llvm-project
[X86] Remove X87 schedule itineraries (PR37093)
First of a number of commits to remove x86 schedule itineraries entirely - approved off-line with @craig.topper llvm-svn: 329893
This commit is contained in:
Simon Pilgrim
parent
34812c0d0d
commit
32d368147f
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@ -118,12 +118,10 @@ let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
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// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
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// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
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// f80 instructions cannot use SSE and use neither of these.
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class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern,
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InstrItinClass itin = NoItinerary> :
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FpI_<outs, ins, fp, pattern, itin>, Requires<[FPStackf32]>;
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class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern,
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InstrItinClass itin = NoItinerary> :
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FpI_<outs, ins, fp, pattern, itin>, Requires<[FPStackf64]>;
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class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
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FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>;
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class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
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FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
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// Factoring for arithmetic.
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multiclass FPBinary_rr<SDNode OpNode> {
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@ -297,30 +295,29 @@ def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">;
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} // SchedRW
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// Unary operations.
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multiclass FPUnary<SDNode OpNode, Format fp, string asmstring,
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InstrItinClass itin> {
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multiclass FPUnary<SDNode OpNode, Format fp, string asmstring> {
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def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
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[(set RFP32:$dst, (OpNode RFP32:$src))], itin>;
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[(set RFP32:$dst, (OpNode RFP32:$src))]>;
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def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
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[(set RFP64:$dst, (OpNode RFP64:$src))], itin>;
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[(set RFP64:$dst, (OpNode RFP64:$src))]>;
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def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
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[(set RFP80:$dst, (OpNode RFP80:$src))], itin>;
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def _F : FPI<0xD9, fp, (outs), (ins), asmstring, itin>;
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[(set RFP80:$dst, (OpNode RFP80:$src))]>;
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def _F : FPI<0xD9, fp, (outs), (ins), asmstring>;
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}
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let Defs = [FPSW] in {
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let SchedRW = [WriteVecLogic] in {
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defm CHS : FPUnary<fneg, MRM_E0, "fchs", IIC_FSIGN>;
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defm ABS : FPUnary<fabs, MRM_E1, "fabs", IIC_FSIGN>;
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defm CHS : FPUnary<fneg, MRM_E0, "fchs">;
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defm ABS : FPUnary<fabs, MRM_E1, "fabs">;
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}
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let SchedRW = [WriteFSqrt] in
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defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt", IIC_FSQRT>;
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defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">;
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let SchedRW = [WriteMicrocoded] in {
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defm SIN : FPUnary<fsin, MRM_FE, "fsin", IIC_FSINCOS>;
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defm COS : FPUnary<fcos, MRM_FF, "fcos", IIC_FSINCOS>;
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defm SIN : FPUnary<fsin, MRM_FE, "fsin">;
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defm COS : FPUnary<fcos, MRM_FF, "fcos">;
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}
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let SchedRW = [WriteFAdd] in {
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@ -330,7 +327,7 @@ def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
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def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
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} // hasSideEffects
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def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst", IIC_FCOMI>;
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def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">;
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} // SchedRW
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} // Defs = [FPSW]
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@ -363,26 +360,24 @@ def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">;
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} // SchedRW
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// Floating point cmovs.
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class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern,
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InstrItinClass itin> :
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FpI_<outs, ins, fp, pattern, itin>, Requires<[FPStackf32, HasCMov]>;
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class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern,
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InstrItinClass itin> :
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FpI_<outs, ins, fp, pattern, itin>, Requires<[FPStackf64, HasCMov]>;
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class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
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FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>;
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class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
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FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>;
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multiclass FPCMov<PatLeaf cc> {
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def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
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CondMovFP,
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[(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
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cc, EFLAGS))], IIC_FCMOV>;
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cc, EFLAGS))]>;
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def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
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CondMovFP,
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[(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
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cc, EFLAGS))], IIC_FCMOV>;
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cc, EFLAGS))]>;
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def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
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CondMovFP,
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[(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
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cc, EFLAGS))], IIC_FCMOV>,
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cc, EFLAGS))]>,
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Requires<[HasCMov]>;
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}
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@ -402,21 +397,21 @@ defm CMOVNP : FPCMov<X86_COND_NP>;
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let Predicates = [HasCMov] in {
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// These are not factored because there's no clean way to pass DA/DB.
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def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RST:$op),
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"fcmovb\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
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"fcmovb\t{$op, %st(0)|st(0), $op}">;
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def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RST:$op),
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"fcmovbe\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
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"fcmovbe\t{$op, %st(0)|st(0), $op}">;
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def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RST:$op),
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"fcmove\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
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"fcmove\t{$op, %st(0)|st(0), $op}">;
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def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RST:$op),
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"fcmovu\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
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"fcmovu\t{$op, %st(0)|st(0), $op}">;
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def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RST:$op),
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"fcmovnb\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
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"fcmovnb\t{$op, %st(0)|st(0), $op}">;
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def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RST:$op),
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"fcmovnbe\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
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"fcmovnbe\t{$op, %st(0)|st(0), $op}">;
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def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RST:$op),
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"fcmovne\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
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"fcmovne\t{$op, %st(0)|st(0), $op}">;
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def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RST:$op),
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"fcmovnu\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
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"fcmovnu\t{$op, %st(0)|st(0), $op}">;
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} // Predicates = [HasCMov]
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} // SchedRW
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@ -495,40 +490,24 @@ def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
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} // SchedRW
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let mayLoad = 1, SchedRW = [WriteLoad] in {
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def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src",
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IIC_FLD>;
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def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src",
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IIC_FLD>;
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def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src",
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IIC_FLD80>;
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def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src",
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IIC_FILD>;
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def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src",
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IIC_FILD>;
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def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src",
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IIC_FILD>;
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def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
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def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
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def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
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def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
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def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
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def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
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}
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let mayStore = 1, SchedRW = [WriteStore] in {
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def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst",
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IIC_FST>;
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def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst",
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IIC_FST>;
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def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst",
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IIC_FST>;
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def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst",
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IIC_FST>;
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def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst",
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IIC_FST80>;
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def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst",
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IIC_FIST>;
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def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst",
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IIC_FIST>;
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def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst",
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IIC_FIST>;
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def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst",
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IIC_FIST>;
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def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst",
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IIC_FIST>;
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def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
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def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
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def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
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def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
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def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
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def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
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def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
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def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
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def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
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def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
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}
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// FISTTP requires SSE3 even though it's a FPStack op.
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@ -554,20 +533,17 @@ def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
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} // Predicates = [HasSSE3]
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let mayStore = 1, SchedRW = [WriteStore] in {
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def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst",
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IIC_FST>;
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def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst",
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IIC_FST>;
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def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst),
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"fisttp{ll}\t$dst", IIC_FST>;
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def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
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def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
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def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
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}
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// FP Stack manipulation instructions.
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let SchedRW = [WriteMove] in {
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def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op", IIC_FLD>;
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def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op", IIC_FST>;
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def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op", IIC_FST>;
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def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op", IIC_FXCH>;
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def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op">;
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def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op">;
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def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op">;
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def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op">;
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}
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// Floating point constant loads.
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@ -587,8 +563,8 @@ def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
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}
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let SchedRW = [WriteZero] in {
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def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz", IIC_FLDZ>;
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def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1", IIC_FIST>;
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def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">;
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def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">;
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}
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// Floating point compares.
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@ -615,25 +591,23 @@ def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
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let Defs = [FPSW], Uses = [ST0] in {
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def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i)
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(outs), (ins RST:$reg), "fucom\t$reg", IIC_FUCOM>;
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(outs), (ins RST:$reg), "fucom\t$reg">;
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def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
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(outs), (ins RST:$reg), "fucomp\t$reg", IIC_FUCOM>;
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(outs), (ins RST:$reg), "fucomp\t$reg">;
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def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop
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(outs), (ins), "fucompp", IIC_FUCOM>;
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(outs), (ins), "fucompp">;
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}
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let Defs = [EFLAGS, FPSW], Uses = [ST0] in {
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def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i)
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(outs), (ins RST:$reg), "fucomi\t$reg", IIC_FUCOMI>;
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(outs), (ins RST:$reg), "fucomi\t$reg">;
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def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop
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(outs), (ins RST:$reg), "fucompi\t$reg", IIC_FUCOMI>;
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(outs), (ins RST:$reg), "fucompi\t$reg">;
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}
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let Defs = [EFLAGS, FPSW] in {
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def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg),
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"fcomi\t$reg", IIC_FCOMI>;
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def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg),
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"fcompi\t$reg", IIC_FCOMI>;
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def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg), "fcomi\t$reg">;
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def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg), "fcompi\t$reg">;
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}
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} // SchedRW
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@ -642,71 +616,69 @@ let SchedRW = [WriteALU] in {
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let Defs = [AX], Uses = [FPSW] in
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def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags
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(outs), (ins), "fnstsw\t{%ax|ax}",
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[(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>;
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[(set AX, (X86fp_stsw FPSW))]>;
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let Defs = [FPSW] in
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def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
|
||||
(outs), (ins i16mem:$dst), "fnstcw\t$dst",
|
||||
[(X86fp_cwd_get16 addr:$dst)], IIC_FNSTCW>;
|
||||
[(X86fp_cwd_get16 addr:$dst)]>;
|
||||
} // SchedRW
|
||||
let Defs = [FPSW], mayLoad = 1 in
|
||||
def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
|
||||
(outs), (ins i16mem:$dst), "fldcw\t$dst", [], IIC_FLDCW>,
|
||||
(outs), (ins i16mem:$dst), "fldcw\t$dst", []>,
|
||||
Sched<[WriteLoad]>;
|
||||
|
||||
// FPU control instructions
|
||||
let SchedRW = [WriteMicrocoded] in {
|
||||
let Defs = [FPSW] in {
|
||||
def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", [], IIC_FNINIT>;
|
||||
def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg),
|
||||
"ffree\t$reg", IIC_FFREE>;
|
||||
def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RST:$reg),
|
||||
"ffreep\t$reg", IIC_FFREE>;
|
||||
def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>;
|
||||
def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), "ffree\t$reg">;
|
||||
def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RST:$reg), "ffreep\t$reg">;
|
||||
|
||||
// Clear exceptions
|
||||
def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>;
|
||||
def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>;
|
||||
} // Defs = [FPSW]
|
||||
} // SchedRW
|
||||
|
||||
// Operand-less floating-point instructions for the disassembler.
|
||||
def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>, Sched<[WriteNop]>;
|
||||
def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>;
|
||||
|
||||
let SchedRW = [WriteMicrocoded] in {
|
||||
let Defs = [FPSW] in {
|
||||
def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>;
|
||||
def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", [], IIC_FXAM>;
|
||||
def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", [], IIC_FLDL>;
|
||||
def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", [], IIC_FLDL>;
|
||||
def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", [], IIC_FLDL>;
|
||||
def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", [], IIC_FLDL>;
|
||||
def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", [], IIC_FLDL>;
|
||||
def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", [], IIC_F2XM1>;
|
||||
def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", [], IIC_FYL2X>;
|
||||
def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", [], IIC_FPTAN>;
|
||||
def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", [], IIC_FPATAN>;
|
||||
def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", [], IIC_FXTRACT>;
|
||||
def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", [], IIC_FPREM1>;
|
||||
def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", [], IIC_FPSTP>;
|
||||
def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", [], IIC_FPSTP>;
|
||||
def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", [], IIC_FPREM>;
|
||||
def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", [], IIC_FYL2XP1>;
|
||||
def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", [], IIC_FSINCOS>;
|
||||
def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", [], IIC_FRNDINT>;
|
||||
def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", [], IIC_FSCALE>;
|
||||
def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", [], IIC_FCOMPP>;
|
||||
def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
|
||||
def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>;
|
||||
def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>;
|
||||
def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>;
|
||||
def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>;
|
||||
def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>;
|
||||
def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>;
|
||||
def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>;
|
||||
def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>;
|
||||
def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>;
|
||||
def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>;
|
||||
def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>;
|
||||
def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>;
|
||||
def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>;
|
||||
def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>;
|
||||
def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>;
|
||||
def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>;
|
||||
def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>;
|
||||
def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>;
|
||||
def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>;
|
||||
def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>;
|
||||
} // Defs = [FPSW]
|
||||
|
||||
def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaque512mem:$dst),
|
||||
"fxsave\t$dst", [(int_x86_fxsave addr:$dst)], IIC_FXSAVE>, TB,
|
||||
"fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB,
|
||||
Requires<[HasFXSR]>;
|
||||
def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaque512mem:$dst),
|
||||
"fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)],
|
||||
IIC_FXSAVE>, TB, Requires<[HasFXSR, In64BitMode]>;
|
||||
"fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>,
|
||||
TB, Requires<[HasFXSR, In64BitMode]>;
|
||||
def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
|
||||
"fxrstor\t$src", [(int_x86_fxrstor addr:$src)], IIC_FXRSTOR>,
|
||||
"fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>,
|
||||
TB, Requires<[HasFXSR]>;
|
||||
def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
|
||||
"fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)],
|
||||
IIC_FXRSTOR>, TB, Requires<[HasFXSR, In64BitMode]>;
|
||||
"fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>,
|
||||
TB, Requires<[HasFXSR, In64BitMode]>;
|
||||
} // SchedRW
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -432,14 +432,12 @@ class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
|
|||
|
||||
// FPStack Instruction Templates:
|
||||
// FPI - Floating Point Instruction template.
|
||||
class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
InstrItinClass itin = NoItinerary>
|
||||
: I<o, F, outs, ins, asm, [], itin> {}
|
||||
class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
|
||||
: I<o, F, outs, ins, asm, []> {}
|
||||
|
||||
// FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
|
||||
class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
|
||||
InstrItinClass itin = NoItinerary>
|
||||
: PseudoI<outs, ins, pattern, itin> {
|
||||
class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
|
||||
: PseudoI<outs, ins, pattern> {
|
||||
let FPForm = fp;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -490,47 +490,6 @@ def IIC_CMPX_LOCK_16B : InstrItinClass;
|
|||
def IIC_XADD_LOCK_MEM : InstrItinClass;
|
||||
def IIC_XADD_LOCK_MEM8 : InstrItinClass;
|
||||
|
||||
def IIC_FCMOV : InstrItinClass;
|
||||
def IIC_FILD : InstrItinClass;
|
||||
def IIC_FLD : InstrItinClass;
|
||||
def IIC_FLD80 : InstrItinClass;
|
||||
def IIC_FST : InstrItinClass;
|
||||
def IIC_FST80 : InstrItinClass;
|
||||
def IIC_FIST : InstrItinClass;
|
||||
def IIC_FLDZ : InstrItinClass;
|
||||
def IIC_FUCOM : InstrItinClass;
|
||||
def IIC_FUCOMI : InstrItinClass;
|
||||
def IIC_FCOMI : InstrItinClass;
|
||||
def IIC_FNSTSW : InstrItinClass;
|
||||
def IIC_FNSTCW : InstrItinClass;
|
||||
def IIC_FLDCW : InstrItinClass;
|
||||
def IIC_FNINIT : InstrItinClass;
|
||||
def IIC_FFREE : InstrItinClass;
|
||||
def IIC_FNCLEX : InstrItinClass;
|
||||
def IIC_WAIT : InstrItinClass;
|
||||
def IIC_FXAM : InstrItinClass;
|
||||
def IIC_FNOP : InstrItinClass;
|
||||
def IIC_FLDL : InstrItinClass;
|
||||
def IIC_F2XM1 : InstrItinClass;
|
||||
def IIC_FYL2X : InstrItinClass;
|
||||
def IIC_FPTAN : InstrItinClass;
|
||||
def IIC_FPATAN : InstrItinClass;
|
||||
def IIC_FXTRACT : InstrItinClass;
|
||||
def IIC_FPREM1 : InstrItinClass;
|
||||
def IIC_FPSTP : InstrItinClass;
|
||||
def IIC_FPREM : InstrItinClass;
|
||||
def IIC_FSIGN : InstrItinClass;
|
||||
def IIC_FSQRT : InstrItinClass;
|
||||
def IIC_FYL2XP1 : InstrItinClass;
|
||||
def IIC_FSINCOS : InstrItinClass;
|
||||
def IIC_FRNDINT : InstrItinClass;
|
||||
def IIC_FSCALE : InstrItinClass;
|
||||
def IIC_FCOMPP : InstrItinClass;
|
||||
def IIC_FXSAVE : InstrItinClass;
|
||||
def IIC_FXRSTOR : InstrItinClass;
|
||||
|
||||
def IIC_FXCH : InstrItinClass;
|
||||
|
||||
// System instructions
|
||||
def IIC_CPUID : InstrItinClass;
|
||||
def IIC_INT : InstrItinClass;
|
||||
|
|
|
|||
Loading…
Reference in New Issue