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[AMDGPU][MC] Enabled parsing of relocations on VALU instructions 

See bug 37566: https://bugs.llvm.org/show_bug.cgi?id=37566

Reviewers: artem.tamazov, arsenm, nhaehnle

Differential Revision: https://reviews.llvm.org/D47884

llvm-svn: 334622
This commit is contained in:
Dmitry Preobrazhensky 2018-06-13 17:02:03 +00:00
parent 54a138a0c5
commit 32c6b5cb70
3 changed files with 20 additions and 2 deletions
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4
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View File

@ -443,7 +443,7 @@ public:
}
bool isVSrcB32() const {
return isVCSrcF32() || isLiteralImm(MVT::i32);
return isVCSrcF32() || isLiteralImm(MVT::i32) || isExpr();
}
bool isVSrcB64() const {
@ -460,7 +460,7 @@ public:
}
bool isVSrcF32() const {
return isVCSrcF32() || isLiteralImm(MVT::f32);
return isVCSrcF32() || isLiteralImm(MVT::f32) || isExpr();
}
bool isVSrcF64() const {

3
llvm/test/MC/AMDGPU/expressions.s
View File

@ -40,6 +40,9 @@ s_mov_b32 s0, foo+2
s_mov_b32 s0, foo+2
// VI: s_mov_b32 s0, 514 ; encoding: [0xff,0x00,0x80,0xbe,0x02,0x02,0x00,0x00]
v_mul_f32 v0, foo+2, v2
// VI: v_mul_f32_e32 v0, 514, v2 ; encoding: [0xff,0x04,0x00,0x0a,0x02,0x02,0x00,0x00]
BB1:
v_nop_e64
BB2:

15
llvm/test/MC/AMDGPU/reloc.s
View File

@ -9,6 +9,13 @@
// CHECK: R_AMDGPU_GOTPCREL32_HI global_var2 0x0
// CHECK: R_AMDGPU_REL32_LO global_var3 0x0
// CHECK: R_AMDGPU_REL32_HI global_var4 0x0
// CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
// CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
// CHECK: R_AMDGPU_GOTPCREL global_var0 0x0
// CHECK: R_AMDGPU_GOTPCREL32_LO global_var1 0x0
// CHECK: R_AMDGPU_GOTPCREL32_HI global_var2 0x0
// CHECK: R_AMDGPU_REL32_LO global_var3 0x0
// CHECK: R_AMDGPU_REL32_HI global_var4 0x0
// CHECK: R_AMDGPU_ABS32 var 0x0
// CHECK: }
// CHECK: .rel.data {
@ -26,6 +33,14 @@ kernel:
s_mov_b32 s5, global_var3@rel32@lo
s_mov_b32 s6, global_var4@rel32@hi
v_mov_b32 v0, SCRATCH_RSRC_DWORD0
v_mov_b32 v1, SCRATCH_RSRC_DWORD1
v_mov_b32 v2, global_var0@GOTPCREL
v_mov_b32 v3, global_var1@gotpcrel32@lo
v_mov_b32 v4, global_var2@gotpcrel32@hi
v_mov_b32 v5, global_var3@rel32@lo
v_mov_b32 v6, global_var4@rel32@hi
.globl global_var0
.globl global_var1
.globl global_var2