forked from OSchip/llvm-project
Regenerate vector sext/zext constant folding tests.
llvm-svn: 259405
This commit is contained in:
Simon Pilgrim
parent
b5a6970ace
commit
32b25549fa
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; Verify that the backend correctly folds a sign/zero extend of a vector where
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@ -6,8 +7,11 @@
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; simple loads from constant pool of the result. That is because the resulting
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; vector should be known at static time.
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define <4 x i16> @test1() {
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; CHECK-LABEL: test1:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [0,4294967295,2,4294967293]
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; CHECK-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 0, i32 0
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%2 = insertelement <4 x i8> %1, i8 -1, i32 1
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%3 = insertelement <4 x i8> %2, i8 2, i32 2
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@ -15,11 +19,12 @@ define <4 x i16> @test1() {
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%5 = sext <4 x i8> %4 to <4 x i16>
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ret <4 x i16> %5
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}
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; CHECK-LABEL: test1
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <4 x i16> @test2() {
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; CHECK-LABEL: test2:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <u,4294967295,u,4294967293>
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; CHECK-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 undef, i32 0
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%2 = insertelement <4 x i8> %1, i8 -1, i32 1
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%3 = insertelement <4 x i8> %2, i8 undef, i32 2
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@ -27,11 +32,12 @@ define <4 x i16> @test2() {
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%5 = sext <4 x i8> %4 to <4 x i16>
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ret <4 x i16> %5
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}
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; CHECK-LABEL: test2
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <4 x i32> @test3() {
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; CHECK-LABEL: test3:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [0,4294967295,2,4294967293]
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; CHECK-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 0, i32 0
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%2 = insertelement <4 x i8> %1, i8 -1, i32 1
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%3 = insertelement <4 x i8> %2, i8 2, i32 2
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@ -39,11 +45,12 @@ define <4 x i32> @test3() {
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%5 = sext <4 x i8> %4 to <4 x i32>
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ret <4 x i32> %5
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}
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; CHECK-LABEL: test3
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <4 x i32> @test4() {
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; CHECK-LABEL: test4:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <u,4294967295,u,4294967293>
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; CHECK-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 undef, i32 0
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%2 = insertelement <4 x i8> %1, i8 -1, i32 1
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%3 = insertelement <4 x i8> %2, i8 undef, i32 2
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@ -51,12 +58,12 @@ define <4 x i32> @test4() {
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%5 = sext <4 x i8> %4 to <4 x i32>
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ret <4 x i32> %5
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}
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; CHECK-LABEL: test4
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <4 x i64> @test5() {
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; CHECK-LABEL: test5:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [0,18446744073709551615,2,18446744073709551613]
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; CHECK-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 0, i32 0
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%2 = insertelement <4 x i8> %1, i8 -1, i32 1
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%3 = insertelement <4 x i8> %2, i8 2, i32 2
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@ -64,12 +71,12 @@ define <4 x i64> @test5() {
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%5 = sext <4 x i8> %4 to <4 x i64>
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ret <4 x i64> %5
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}
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; CHECK-LABEL: test5
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; CHECK-NOT: vinsertf128
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <4 x i64> @test6() {
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; CHECK-LABEL: test6:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = <u,18446744073709551615,u,18446744073709551613>
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; CHECK-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 undef, i32 0
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%2 = insertelement <4 x i8> %1, i8 -1, i32 1
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%3 = insertelement <4 x i8> %2, i8 undef, i32 2
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@ -77,12 +84,12 @@ define <4 x i64> @test6() {
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%5 = sext <4 x i8> %4 to <4 x i64>
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ret <4 x i64> %5
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}
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; CHECK-LABEL: test6
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; CHECK-NOT: vinsertf128
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <8 x i16> @test7() {
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; CHECK-LABEL: test7:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <0,65535,2,65533,u,u,u,u>
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; CHECK-NEXT: retq
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%1 = insertelement <8 x i8> undef, i8 0, i32 0
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%2 = insertelement <8 x i8> %1, i8 -1, i32 1
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%3 = insertelement <8 x i8> %2, i8 2, i32 2
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@ -94,11 +101,12 @@ define <8 x i16> @test7() {
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%9 = sext <8 x i8> %4 to <8 x i16>
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ret <8 x i16> %9
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}
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; CHECK-LABEL: test7
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <8 x i32> @test8() {
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; CHECK-LABEL: test8:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = <0,4294967295,2,4294967293,u,u,u,u>
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; CHECK-NEXT: retq
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%1 = insertelement <8 x i8> undef, i8 0, i32 0
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%2 = insertelement <8 x i8> %1, i8 -1, i32 1
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%3 = insertelement <8 x i8> %2, i8 2, i32 2
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@ -110,12 +118,12 @@ define <8 x i32> @test8() {
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%9 = sext <8 x i8> %4 to <8 x i32>
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ret <8 x i32> %9
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}
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; CHECK-LABEL: test8
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; CHECK-NOT: vinsertf128
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <8 x i16> @test9() {
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; CHECK-LABEL: test9:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <u,65535,u,65533,u,u,u,u>
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; CHECK-NEXT: retq
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%1 = insertelement <8 x i8> undef, i8 undef, i32 0
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%2 = insertelement <8 x i8> %1, i8 -1, i32 1
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%3 = insertelement <8 x i8> %2, i8 undef, i32 2
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@ -127,11 +135,12 @@ define <8 x i16> @test9() {
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%9 = sext <8 x i8> %4 to <8 x i16>
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ret <8 x i16> %9
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}
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; CHECK-LABEL: test9
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <8 x i32> @test10() {
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; CHECK-LABEL: test10:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = <0,u,2,u,u,u,u,u>
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; CHECK-NEXT: retq
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%1 = insertelement <8 x i8> undef, i8 0, i32 0
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%2 = insertelement <8 x i8> %1, i8 undef, i32 1
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%3 = insertelement <8 x i8> %2, i8 2, i32 2
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@ -143,13 +152,12 @@ define <8 x i32> @test10() {
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%9 = sext <8 x i8> %4 to <8 x i32>
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ret <8 x i32> %9
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}
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; CHECK-LABEL: test10
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; CHECK-NOT: vinsertf128
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <4 x i16> @test11() {
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; CHECK-LABEL: test11:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,2,253]
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; CHECK-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 0, i32 0
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%2 = insertelement <4 x i8> %1, i8 -1, i32 1
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%3 = insertelement <4 x i8> %2, i8 2, i32 2
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@ -157,11 +165,12 @@ define <4 x i16> @test11() {
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%5 = zext <4 x i8> %4 to <4 x i16>
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ret <4 x i16> %5
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}
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; CHECK-LABEL: test11
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <4 x i32> @test12() {
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; CHECK-LABEL: test12:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,2,253]
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; CHECK-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 0, i32 0
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%2 = insertelement <4 x i8> %1, i8 -1, i32 1
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%3 = insertelement <4 x i8> %2, i8 2, i32 2
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@ -169,11 +178,12 @@ define <4 x i32> @test12() {
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%5 = zext <4 x i8> %4 to <4 x i32>
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ret <4 x i32> %5
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}
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; CHECK-LABEL: test12
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <4 x i64> @test13() {
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; CHECK-LABEL: test13:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,2,253]
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; CHECK-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 0, i32 0
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%2 = insertelement <4 x i8> %1, i8 -1, i32 1
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%3 = insertelement <4 x i8> %2, i8 2, i32 2
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@ -181,12 +191,12 @@ define <4 x i64> @test13() {
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%5 = zext <4 x i8> %4 to <4 x i64>
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ret <4 x i64> %5
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}
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; CHECK-LABEL: test13
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; CHECK-NOT: vinsertf128
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <4 x i16> @test14() {
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; CHECK-LABEL: test14:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <u,255,u,253>
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; CHECK-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 undef, i32 0
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%2 = insertelement <4 x i8> %1, i8 -1, i32 1
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%3 = insertelement <4 x i8> %2, i8 undef, i32 2
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@ -194,11 +204,12 @@ define <4 x i16> @test14() {
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%5 = zext <4 x i8> %4 to <4 x i16>
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ret <4 x i16> %5
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}
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; CHECK-LABEL: test14
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <4 x i32> @test15() {
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; CHECK-LABEL: test15:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <0,u,2,u>
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; CHECK-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 0, i32 0
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%2 = insertelement <4 x i8> %1, i8 undef, i32 1
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%3 = insertelement <4 x i8> %2, i8 2, i32 2
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@ -206,11 +217,12 @@ define <4 x i32> @test15() {
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%5 = zext <4 x i8> %4 to <4 x i32>
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ret <4 x i32> %5
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}
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; CHECK-LABEL: test15
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <4 x i64> @test16() {
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; CHECK-LABEL: test16:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = <u,255,2,u>
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; CHECK-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 undef, i32 0
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%2 = insertelement <4 x i8> %1, i8 -1, i32 1
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%3 = insertelement <4 x i8> %2, i8 2, i32 2
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@ -218,12 +230,12 @@ define <4 x i64> @test16() {
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%5 = zext <4 x i8> %4 to <4 x i64>
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ret <4 x i64> %5
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}
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; CHECK-LABEL: test16
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; CHECK-NOT: vinsertf128
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <8 x i16> @test17() {
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; CHECK-LABEL: test17:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,2,253,4,251,6,249]
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; CHECK-NEXT: retq
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%1 = insertelement <8 x i8> undef, i8 0, i32 0
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%2 = insertelement <8 x i8> %1, i8 -1, i32 1
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%3 = insertelement <8 x i8> %2, i8 2, i32 2
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@ -235,11 +247,12 @@ define <8 x i16> @test17() {
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%9 = zext <8 x i8> %8 to <8 x i16>
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ret <8 x i16> %9
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}
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; CHECK-LABEL: test17
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <8 x i32> @test18() {
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; CHECK-LABEL: test18:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,2,253,4,251,6,249]
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; CHECK-NEXT: retq
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%1 = insertelement <8 x i8> undef, i8 0, i32 0
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%2 = insertelement <8 x i8> %1, i8 -1, i32 1
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%3 = insertelement <8 x i8> %2, i8 2, i32 2
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@ -251,12 +264,12 @@ define <8 x i32> @test18() {
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%9 = zext <8 x i8> %8 to <8 x i32>
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ret <8 x i32> %9
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}
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; CHECK-LABEL: test18
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; CHECK-NOT: vinsertf128
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <8 x i16> @test19() {
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; CHECK-LABEL: test19:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <u,255,u,253,u,251,u,249>
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; CHECK-NEXT: retq
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%1 = insertelement <8 x i8> undef, i8 undef, i32 0
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%2 = insertelement <8 x i8> %1, i8 -1, i32 1
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%3 = insertelement <8 x i8> %2, i8 undef, i32 2
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@ -268,11 +281,12 @@ define <8 x i16> @test19() {
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%9 = zext <8 x i8> %8 to <8 x i16>
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ret <8 x i16> %9
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}
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; CHECK-LABEL: test19
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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define <8 x i32> @test20() {
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; CHECK-LABEL: test20:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = <0,u,2,253,4,u,6,u>
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; CHECK-NEXT: retq
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%1 = insertelement <8 x i8> undef, i8 0, i32 0
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%2 = insertelement <8 x i8> %1, i8 undef, i32 1
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%3 = insertelement <8 x i8> %2, i8 2, i32 2
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@ -284,8 +298,3 @@ define <8 x i32> @test20() {
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%9 = zext <8 x i8> %8 to <8 x i32>
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ret <8 x i32> %9
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}
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; CHECK-LABEL: test20
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; CHECK-NOT: vinsertf128
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; CHECK: vmovaps
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; CHECK-NEXT: ret
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