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[X86][SSE] detectAVGPattern - begin generalizing ADD matches 

Move the ADD matching into a helper - first NFC stage towards supporting 'ADD like' cases such as in PR41316

llvm-svn: 357349
This commit is contained in:
Simon Pilgrim 2019-03-30 15:31:53 +00:00
parent 7dd1c36cd7
commit 3293455595
1 changed files with 15 additions and 4 deletions
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19
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -38203,12 +38203,23 @@ static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
AVGBuilder);
}
if (Operands[0].getOpcode() == ISD::ADD)
// Matches 'add like' patterns.
// TODO: Extend this to include or/zext cases.
auto FindAddLike = [&](SDValue V, SDValue &Op0, SDValue &Op1) {
if (ISD::ADD != V.getOpcode())
return false;
Op0 = V.getOperand(0);
Op1 = V.getOperand(1);
return true;
};
SDValue Op0, Op1;
if (FindAddLike(Operands[0], Op0, Op1))
std::swap(Operands[0], Operands[1]);
else if (Operands[1].getOpcode() != ISD::ADD)
else if (!FindAddLike(Operands[1], Op0, Op1))
return SDValue();
Operands[2] = Operands[1].getOperand(0);
Operands[1] = Operands[1].getOperand(1);
Operands[2] = Op0;
Operands[1] = Op1;
// Now we have three operands of two additions. Check that one of them is a
// constant vector with ones, and the other two are promoted from i8/i16.